Henry Hsieh 58d50a0e97 riscv: fix non-standard assembly of RISC-V ... Non-standard `jalr rd, rs` pseudo-instructions are used. This commit changes them to `ret` for standard return pseudo-instruction or `jalr rd, rs, 0` for no offset jump register and link. Fixes #41100. Signed-off-by: Henry Hsieh <r901042004@yahoo.com.tw>		2022-02-04 11:23:39 +01:00
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core	riscv: fix non-standard assembly of RISC-V	2022-02-04 11:23:39 +01:00
include	arch: riscv: pmp: add PMP protection of code and rodata	2022-01-11 11:47:03 +01:00
CMakeLists.txt	riscv: toolchain arguments for a 64-bit build	2019-08-09 09:11:45 -05:00
Kconfig	arch: riscv: pmp: add PMP protection of code and rodata	2022-01-11 11:47:03 +01:00