zephyr/dts/riscv
Franciszek Zdobylak 8a9be6eb0d dts: riscv: sifive: fu740: add more cpus
Update devicetree to support more cpus.

Signed-off-by: Franciszek Zdobylak <fzdobylak@antmicro.com>
2023-04-12 13:06:29 +02:00
..
andes dts: bindings: spi: add andes spi driver 2022-09-07 15:34:47 +02:00
espressif drivers: spi: esp32xx: refactor SPI DMA preprocessor identifiers 2023-03-13 14:02:06 +01:00
gigadevice dts: bindings: gd32-dma-base: add gd,mem2mem property 2022-12-22 13:43:49 +01:00
ite ITE drivers/pinctrl/it8xxx2: add default mode function 2023-02-19 21:00:14 -05:00
lowrisc boards: riscv: Add initial support for OpenTitan Earl Grey 2023-01-27 19:25:26 +09:00
microsemi dts: riscv: microsemi-miv: define CLINT 2022-08-02 09:12:31 +02:00
niosv dts: riscv: Add dts support for INTEL NIOSV 2023-02-20 09:29:13 -05:00
openisa dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
sifive dts: riscv: sifive: fu740: add more cpus 2023-04-12 13:06:29 +02:00
starfive dts: riscv: starfive: align clint description with Linux 2022-08-02 09:12:31 +02:00
telink dts: riscv: telink: add DT entry for machine timer 2022-08-02 09:12:31 +02:00
mpfs-icicle.dtsi dts: mpfs_icicle: add all uart nodes to the Devicetree 2023-03-21 13:39:52 +01:00
neorv32.dtsi dts: riscv: neorv32: define machine timer 2022-08-02 09:12:31 +02:00
riscv32-litex-vexriscv.dtsi dts: riscv: Remove label property from devicetrees 2022-07-26 12:57:23 -05:00
virt.dtsi dts: riscv: virt: use sifive,clint0 2022-08-02 09:12:31 +02:00