09e2a4e9eb
Add ipm driver to use Inter Processor Interrupts on Xilinx ZynqMP platform. This patch also adds sample application that shows use of xlnx ipm driver. This driver uses default arm gic interrupt controller and works only for lockstep mode of cortex-r5f cluster for now. In split mode the cortex-r5 cluster will have two r5f cores and they are expected to work in AMP mode. If both r5f cores run simultaneouly, only one of the core is able to receive IPI interrupts at this time and it will be the one that started later. In future this limitation shall be removed. Signed-off-by: Tanmay Shah <tanmay.shah@amd.com>
32 lines
626 B
C
32 lines
626 B
C
/*
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* Copyright (c) 2023, Advanced Micro Devices Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _IPM_XLNX_IPI_H_
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#define _IPM_XLNX_IPI_H_
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/* IPI Channel ID bits */
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#define IPI_CH0_BIT 0
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#define IPI_CH1_BIT 8
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#define IPI_CH2_BIT 9
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#define IPI_CH3_BIT 16
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#define IPI_CH4_BIT 17
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#define IPI_CH5_BIT 18
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#define IPI_CH6_BIT 19
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#define IPI_CH7_BIT 24
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#define IPI_CH8_BIT 25
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#define IPI_CH9_BIT 26
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#define IPI_CH10_BIT 27
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/* Register offsets */
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#define IPI_TRIG 0x00
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#define IPI_OBS 0x04
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#define IPI_ISR 0x10
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#define IPI_IMR 0x14
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#define IPI_IER 0x18
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#define IPI_IDR 0x1C
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#endif /* _IPM_XLNX_IPI_H_ */
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