zephyr/dts/xtensa
Tomasz Leman 9656056b19 dts: adsp: ace20: remove lp clock
LP/HP RING OSC clocks were replaced by the ACE IPLL clock.

If needed IPLL can be configured to work as low power clock. But right
now ACE uses only WOVCRO and IPLL (configured to work as HP RING OSC
clock).

Signed-off-by: Tomasz Leman <tomasz.m.leman@intel.com>
2023-09-18 10:35:23 +01:00
..
espressif soc: esp32s3: add ADC single-shot support 2023-08-17 10:36:20 +02:00
intel dts: adsp: ace20: remove lp clock 2023-09-18 10:35:23 +01:00
nxp dts: xtensa: nxp: add nodes for IPC 2023-07-26 14:33:36 +02:00
dc233c.dtsi xtensa: dc233c: enlarge ROM space 2023-09-14 17:07:21 -04:00
sample_controller.dtsi dts: Add information about CPU frequency to the cpu nodes 2019-07-17 21:53:36 +02:00
xtensa.dtsi dts: Restructure xtensa dts directory 2019-06-27 07:21:11 -04:00