a8af622f68
When exiting PM_STATE_SOFT_OFF, the primary core state is always used to restore bootctl register and the clock and power gating settings. This can lead to problems if non-primary core is powered up and down many times before primary core 0 is powered down the first time. The saved state in core_desc[0].bctl will be null, and as a result- power gating and clock gating is not disabled correctly for non-primary cores. Link: https://github.com/thesofproject/sof/issues/8642 Signed-off-by: Kai Vehmanen <kai.vehmanen@linux.intel.com> |
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| .. | ||
| dc233c | ||
| espressif_esp32 | ||
| intel_adsp | ||
| nxp_adsp | ||
| sample_controller | ||
| CMakeLists.txt | ||