Filip Kokosinski 6297f3640f dts/riscv/andes: add andestech,andescore-v5 compatible string ... This commit adds the `andestech,andescore-v5` compatible string. This helps identify the core tpye form the final devicetree alone. Andes doesn't define which core type from the v5 series the AE350 SoC uses, so we're using the whole series name here. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>		2024-01-31 10:41:49 +01:00
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andes_v5_ae350.dtsi	dts/riscv/andes: add andestech,andescore-v5 compatible string	2024-01-31 10:41:49 +01:00