99f211b668
To allow transition to device tree based clock configuration on stm32 targets, rework clock_control driver to use intermediate STM32_ macros initially defined as the equivalent Kconfig macros for now. Propagate the change in all code using these macros. The reason to introduce these new macros instead of configuring Kconfig flags using dt kconfigfunctions is that we'll need to be able to inform users that Kconfig flags are deprecated once the whole family conversion is done, to encourage out of tree users to adopt this new configuration scheme. Note: For now STM32H7 series and code is excluded. This is the same for some series specific code such as PLL mul/div for L0/L1 and XTRE prescaler on F1 series. Signed-off-by: Erwan Gouriou <erwan.gouriou@linaro.org>
56 lines
1.1 KiB
C
56 lines
1.1 KiB
C
/*
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*
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* Copyright (c) 2019 Ilya Tagunov
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* Copyright (c) 2019 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <drivers/clock_control.h>
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#include <sys/util.h>
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#include <drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if STM32_SYSCLK_SRC_PLL
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/* Macros to fill up multiplication and division factors values */
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#define z_pll_div(v) LL_RCC_PLLM_DIV_ ## v
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#define pll_div(v) z_pll_div(v)
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#define z_pllr(v) LL_RCC_PLLR_DIV_ ## v
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#define pllr(v) z_pllr(v)
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/**
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* @brief Fill PLL configuration structure
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*/
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void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
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{
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pllinit->PLLN = STM32_PLL_N_MULTIPLIER;
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pllinit->PLLM = pll_div(STM32_PLL_M_DIVISOR);
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pllinit->PLLR = pllr(STM32_PLL_R_DIVISOR);
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}
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#endif /* STM32_SYSCLK_SRC_PLL */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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}
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/**
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* @brief Function kept for driver genericity
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*/
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void LL_RCC_MSI_Disable(void)
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{
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/* Do nothing */
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}
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