81f0acd5d4
Device tree for Intel SoCFPGA Agilex5 initial bring up. This is the first version of device tree which enable four cores SMP and basic drivers that needed by 'hello_world' and 'cli' applications. Signed-off-by: Girisha Dengi <girisha.dengi@intel.com>
24 lines
575 B
YAML
24 lines
575 B
YAML
# Copyright (c) 2019 Nordic Semiconductor ASA
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
# Common fields for CPUs
|
|
|
|
include: base.yaml
|
|
|
|
properties:
|
|
clock-frequency:
|
|
type: int
|
|
description: Clock frequency in Hz
|
|
cpu-power-states:
|
|
type: phandles
|
|
description: List of power management states supported by this cpu
|
|
i-cache-line-size:
|
|
type: int
|
|
description: i-cache line size
|
|
d-cache-line-size:
|
|
type: int
|
|
description: d-cache line size
|
|
enable-method:
|
|
type: string
|
|
description: Enable method for cpu, either it is "psci" or "spin-table"
|