5670bad505
According to the reference manual the overdrive should be enabled after setup of the sysclock (HSE or HSI) and enabling the PLL (PLLON). The flash latency should be enabled after the PLL has been turned on, but before switching the system clock to the PLL. Signed-off-by: Max van Kessel <max_van_kessel@msn.com>
127 lines
3.1 KiB
C
127 lines
3.1 KiB
C
/*
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*
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* Copyright (c) 2017 Linaro Limited.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if defined(STM32_PLL_ENABLED)
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/**
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* @brief Return PLL source
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*/
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__unused
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static uint32_t get_pll_source(void)
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{
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return LL_RCC_PLLSOURCE_HSI;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return LL_RCC_PLLSOURCE_HSE;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief get the pll source frequency
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*/
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__unused
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uint32_t get_pllsrc_frequency(void)
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{
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return STM32_HSI_FREQ;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return STM32_HSE_FREQ;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief Set up pll configuration
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*/
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__unused
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void config_pll_sysclock(void)
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{
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LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
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pllm(STM32_PLL_M_DIVISOR),
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STM32_PLL_N_MULTIPLIER,
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pllp(STM32_PLL_P_DIVISOR));
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#if defined(CONFIG_SOC_SERIES_STM32F7X)
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/* Assuming we stay on Power Scale default value: Power Scale 1 */
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if (CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC > 180000000) {
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/* Enable the PLL (PLLON) before setting overdrive. Skipping the PLL
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* locking phase since the system will be stalled during the switch
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* (ODSW) but the PLL clock system will be running during the locking
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* phase. See reference manual (RM0431) §4.1.4 Voltage regulator
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* Sub section: Entering Over-drive mode.
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*/
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LL_RCC_PLL_Enable();
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/* Set Overdrive if needed before configuring the Flash Latency */
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LL_PWR_EnableOverDriveMode();
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while (LL_PWR_IsActiveFlag_OD() != 1) {
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/* Wait for OverDrive mode ready */
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}
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LL_PWR_EnableOverDriveSwitching();
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while (LL_PWR_IsActiveFlag_ODSW() != 1) {
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/* Wait for OverDrive switch ready */
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}
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/* The PLL could still not be locked when returning to the caller
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* function. But the caller doesn't know we've turned on the PLL
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* for the overdrive function. The caller will try to turn on the PLL
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* And start waiting for the PLL locking phase to complete.
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*/
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}
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#endif /* CONFIG_SOC_SERIES_STM32F7X */
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}
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#endif /* defined(STM32_PLL_ENABLED) */
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#ifdef STM32_PLLI2S_ENABLED
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/**
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* @brief Set up PLL I2S configuration
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*/
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__unused
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void config_plli2s(void)
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{
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#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32f4_plli2s_clock)
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LL_RCC_PLLI2S_ConfigDomain_I2S(get_pll_source(),
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pllm(STM32_PLLI2S_M_DIVISOR),
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STM32_PLLI2S_N_MULTIPLIER,
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plli2sr(STM32_PLLI2S_R_DIVISOR));
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#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32f412_plli2s_clock)
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LL_RCC_PLL_ConfigDomain_I2S(get_pll_source(),
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plli2sm(STM32_PLLI2S_M_DIVISOR),
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STM32_PLLI2S_N_MULTIPLIER,
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plli2sr(STM32_PLLI2S_R_DIVISOR));
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#endif
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}
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#endif /* STM32_PLLI2S_ENABLED */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Power Interface clock enabled by default */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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}
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