5dad944351
The NXP S32 QSPI controller acts as an interface to up to two serial flash memory devices, each with up to eight bidirectional data lines, depending on the platform. It is based on a LUT enginee to interface through commands with different memory types including flash NOR and Hyperram. This patch adds support for the QSPI in S32K344 which supports a single memory device (side A) with up to four bidirectional data lines and SDR only. Nevertheless, the memory controller is implemented flexible enough to be extended to support more feature-rich QSPI blocks. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
30 lines
624 B
C
30 lines
624 B
C
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <sys/types.h>
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#include <Qspi_Ip.h>
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/**
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* @brief Build a QSPI Look-up Table (LUT) sequence entry.
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*
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* @param inst instruction
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* @param pads pad information
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* @param op operand
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*/
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#define QSPI_LUT_OP(inst, pads, op) \
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((Qspi_Ip_InstrOpType)((Qspi_Ip_InstrOpType)(inst) \
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| (Qspi_Ip_InstrOpType)(pads) \
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| (Qspi_Ip_InstrOpType)(op)))
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/**
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* @brief Get the QSPI peripheral hardware instance number.
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*
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* @param dev device pointer
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*/
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uint8_t memc_nxp_s32_qspi_get_instance(const struct device *dev);
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