b0a5492026
The default is that the high time for open-drain clk is one PPBAUD, which is typically very short. Some device require a longer high time during the open-drain address phase so add a property to allow device tree to override the default. Signed-off-by: Mike J. Chen <mjchen@google.com>
48 lines
1 KiB
YAML
48 lines
1 KiB
YAML
# Copyright (c) 2019 NXP
|
|
# Copyright (c) 2022 Intel Corporation
|
|
#
|
|
# SPDX-License-Identifier: Apache-2.0
|
|
|
|
description: NXP MCUX I3C controller
|
|
|
|
compatible: "nxp,mcux-i3c"
|
|
|
|
include: [i3c-controller.yaml, pinctrl-device.yaml]
|
|
|
|
properties:
|
|
reg:
|
|
required: true
|
|
|
|
interrupts:
|
|
required: true
|
|
|
|
i3c-od-scl-hz:
|
|
type: int
|
|
description: |
|
|
Open Drain Frequency for the I3C controller. When undefined, use
|
|
the controller default or as specified by the I3C specification.
|
|
|
|
clk-divider:
|
|
type: int
|
|
description: Main clock divider for I3C
|
|
required: true
|
|
|
|
clk-divider-tc:
|
|
type: int
|
|
description: TC clock divider for I3C
|
|
required: true
|
|
|
|
clk-divider-slow:
|
|
type: int
|
|
description: Slow clock divider for I3C
|
|
required: true
|
|
|
|
disable-open-drain-high-pp:
|
|
type: boolean
|
|
description: |
|
|
If false, open drain high time is 1 PPBAUD count,
|
|
which is short high and long low.
|
|
If true, open drain high time is same as ODBAUD
|
|
so that open drain clock is 50% duty cycle.
|
|
Default is false.
|