9eef764c65
Refactors all of the DAC drivers to use a shared driver class initialization priority configuration, CONFIG_DAC_INIT_PRIORITY, to allow configuring DAC drivers separately from other devices. This is similar to other driver classes like I2C and SPI. The default is set to CONFIG_KERNEL_INIT_PRIORITY_DEVICE to preserve the existing default initialization priority for most drivers. The exceptions are dacx0508, dacx3608, and mcp4725 drivers which have dependencies on SPI or I2C drivers and must therefore initialize later than the default device priority. Signed-off-by: Maureen Helm <maureen.helm@intel.com>
115 lines
2.9 KiB
C
115 lines
2.9 KiB
C
/*
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* Copyright (c) 2020 Google LLC.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT atmel_sam0_dac
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#include <errno.h>
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#include <drivers/dac.h>
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#include <soc.h>
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/*
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* Maps between the DTS reference property names and register values. Note that
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* the ASF uses the 09/2015 names which differ from the 03/2020 datasheet.
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*
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* TODO(#21273): replace once improved support for enum values lands.
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*/
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#define SAM0_DAC_REFSEL_0 DAC_CTRLB_REFSEL_INT1V_Val
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#define SAM0_DAC_REFSEL_1 DAC_CTRLB_REFSEL_AVCC_Val
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#define SAM0_DAC_REFSEL_2 DAC_CTRLB_REFSEL_VREFP_Val
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struct dac_sam0_cfg {
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Dac *regs;
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uint8_t pm_apbc_bit;
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uint8_t gclk_clkctrl_id;
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uint8_t refsel;
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};
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#define DEV_CFG(dev) ((const struct dac_sam0_cfg *const)(dev)->config)
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/* Write to the DAC. */
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static int dac_sam0_write_value(const struct device *dev, uint8_t channel,
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uint32_t value)
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{
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const struct dac_sam0_cfg *const cfg = DEV_CFG(dev);
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Dac *regs = cfg->regs;
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regs->DATA.reg = (uint16_t)value;
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return 0;
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}
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/*
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* Setup the channel. As the SAM0 has one fixed width channel, this validates
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* the input and does nothing else.
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*/
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static int dac_sam0_channel_setup(const struct device *dev,
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const struct dac_channel_cfg *channel_cfg)
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{
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if (channel_cfg->channel_id != 0) {
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return -EINVAL;
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}
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if (channel_cfg->resolution != 10) {
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return -ENOTSUP;
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}
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return 0;
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}
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/* Initialise and enable the DAC. */
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static int dac_sam0_init(const struct device *dev)
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{
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const struct dac_sam0_cfg *const cfg = DEV_CFG(dev);
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Dac *regs = cfg->regs;
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/* Enable the GCLK */
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GCLK->CLKCTRL.reg = cfg->gclk_clkctrl_id | GCLK_CLKCTRL_GEN_GCLK0 |
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GCLK_CLKCTRL_CLKEN;
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/* Enable the clock in PM */
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PM->APBCMASK.reg |= 1 << cfg->pm_apbc_bit;
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/* Reset then configure the DAC */
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regs->CTRLA.bit.SWRST = 1;
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while (regs->STATUS.bit.SYNCBUSY) {
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}
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regs->CTRLB.bit.REFSEL = cfg->refsel;
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regs->CTRLB.bit.EOEN = 1;
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/* Enable */
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regs->CTRLA.bit.ENABLE = 1;
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while (regs->STATUS.bit.SYNCBUSY) {
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}
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return 0;
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}
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static const struct dac_driver_api api_sam0_driver_api = {
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.channel_setup = dac_sam0_channel_setup,
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.write_value = dac_sam0_write_value
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};
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#define SAM0_DAC_REFSEL(n) \
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COND_CODE_1(DT_INST_NODE_HAS_PROP(n, reference), \
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(DT_ENUM_IDX(DT_DRV_INST(n), reference)), (0))
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#define SAM0_DAC_INIT(n) \
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static const struct dac_sam0_cfg dac_sam0_cfg_##n = { \
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.regs = (Dac *)DT_INST_REG_ADDR(n), \
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.pm_apbc_bit = DT_INST_CLOCKS_CELL_BY_NAME(n, pm, bit), \
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.gclk_clkctrl_id = \
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DT_INST_CLOCKS_CELL_BY_NAME(n, gclk, clkctrl_id), \
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.refsel = UTIL_CAT(SAM0_DAC_REFSEL_, SAM0_DAC_REFSEL(n)), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, &dac_sam0_init, NULL, NULL, \
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&dac_sam0_cfg_##n, POST_KERNEL, \
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CONFIG_DAC_INIT_PRIORITY, \
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&api_sam0_driver_api)
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DT_INST_FOREACH_STATUS_OKAY(SAM0_DAC_INIT);
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