a0a03d7597
This PR includes the required changes in order to support conditional compilation for Armv8-M architecture. Two variants of the Armv8-M architecture are defined: - the Armv8-M Baseline (backwards compatible with ARMv6-M), - the Armv8-M Mainline (backwards compatible with ARMv7-M). Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no>
47 lines
1 KiB
C
47 lines
1 KiB
C
/*
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* Copyright (c) 2015 Intel corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file Software interrupts utility code - ARM implementation
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*/
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#include <kernel.h>
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#include <irq_offload.h>
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volatile irq_offload_routine_t offload_routine;
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static void *offload_param;
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/* Called by __svc */
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void _irq_do_offload(void)
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{
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offload_routine(offload_param);
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}
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void irq_offload(irq_offload_routine_t routine, void *parameter)
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{
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#if defined(CONFIG_ARMV6_M_ARMV8_M_BASELINE) && defined(CONFIG_ASSERT)
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/* Cortex M0 hardfaults if you make a SVC call with interrupts
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* locked.
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*/
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unsigned int key;
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__asm__ volatile("mrs %0, PRIMASK;" : "=r" (key) : : "memory");
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__ASSERT(key == 0, "irq_offload called with interrupts locked\n");
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#endif /* CONFIG_ARMV6_M_ARMV8_M_BASELINE && CONFIG_ASSERT */
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k_sched_lock();
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offload_routine = routine;
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offload_param = parameter;
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__asm__ volatile ("svc %[id]"
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:
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: [id] "i" (_SVC_CALL_IRQ_OFFLOAD)
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: "memory");
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offload_routine = NULL;
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k_sched_unlock();
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}
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