a0a861bfd7
When the counter reaches zero, it reloads the value in SYST_RVR on the next clock edge. This means that if the LOAD value is N, the interrupt ("tick") is triggered every N+1 cycles. Therefore, when we operate in tickless mode, and we want to schedule the next timeout, we need to configure the LOAD value with last_load - 1, in order to get an event in last_load cycles. Signed-off-by: Ioannis Glaropoulos <Ioannis.Glaropoulos@nordicsemi.no> |
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altera_avalon_timer_hal.c | ||
arcv2_timer0.c | ||
CMakeLists.txt | ||
cortex_m_systick.c | ||
hpet.c | ||
Kconfig | ||
legacy_api.h | ||
loapic_timer.c | ||
native_posix_timer.c | ||
nrf_rtc_timer.c | ||
riscv_machine_timer.c | ||
rv32m1_lptmr_timer.c | ||
sam0_rtc_timer.c | ||
sys_clock_init.c | ||
xtensa_sys_timer.c |