b687d76d09
Add infineon xmc series with XMC4500 support. XMC series comes with, - CPU operates upto 120MHz - 3 RAM (PSRAM1 - code, DSRAM1 - data and DSRAM2 - communiation) - upto 1MB flash init: clock control & gpio is not done, so SoC initialization directly relies on HAL. Core operating clock is stored in no_init section, which is kept under DSRAM1. Only DSRAM1 is used until clock support. Using PSRAM1 and DSRAM1 needs adaptation in linker script - planned for next revision. Note: SystemInit cannot be consumed directly due to vector table + HAL linker dependency. Signed-off-by: Parthiban Nallathambi <parthiban@linumiz.com>
19 lines
339 B
Plaintext
19 lines
339 B
Plaintext
# SPDX-License-Identifier: Apache-2.0
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#
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# Copyright (c) 2020 Linumiz
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# Author: Parthiban Nallathambi <parthiban@linumiz.com>
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config HAS_XMCLIB
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bool
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select HAS_CMSIS_CORE
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depends on SOC_FAMILY_XMC
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if HAS_XMCLIB
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config HAS_XMCLIB_UART
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bool
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help
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Enable XMCLIB Universal asynchronous receiver transmitter (UART)
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endif # HAS_XMCLIB
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