589f3f435b
To accommodate support for S32K1 devices, it is necessary to rename the existing `s32k` directory, which currently houses support for the S32K3 series, to align with the respective series names. This adjustment is necessary given the distinct differences in core architecture, MPU, peripherals, and other key aspects between the two series. Signed-off-by: Manuel Argüelles <manuel.arguelles@nxp.com>
44 lines
881 B
C
44 lines
881 B
C
/*
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* Copyright 2023 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/devicetree.h>
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#include <zephyr/linker/devicetree_regions.h>
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#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
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#if !defined(CONFIG_XIP)
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extern char _rom_attr[];
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#endif
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static struct arm_mpu_region mpu_regions[] = {
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/* Keep before CODE region so it can be overlapped by SRAM CODE in non-XIP systems */
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{
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.name = "SRAM",
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.base = CONFIG_SRAM_BASE_ADDRESS,
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.attr = REGION_RAM_ATTR(REGION_SRAM_SIZE),
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},
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#ifdef CONFIG_XIP
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{
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.name = "FLASH",
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.base = CONFIG_FLASH_BASE_ADDRESS,
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.attr = REGION_FLASH_ATTR(REGION_FLASH_SIZE),
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},
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#else
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/* Run from SRAM */
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{
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.name = "CODE",
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.base = CONFIG_SRAM_BASE_ADDRESS,
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.attr = {(uint32_t)_rom_attr},
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},
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#endif
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};
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const struct arm_mpu_config mpu_config = {
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.num_regions = ARRAY_SIZE(mpu_regions),
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.mpu_regions = mpu_regions,
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};
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