zephyr/soc/riscv/espressif_esp32
Gerard Marull-Paretas 68799d507d arch: riscv: make __soc_is_irq optional
It looks like all SoCs in tree check if an exception comes from an IRQ
the same way, so let's provide a common logic by default, still
customizable if the SoC selects RISCV_SOC_ISR_CHECK.

Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
2024-01-23 09:57:57 +01:00
..
common soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00
esp32c3 arch: riscv: make __soc_is_irq optional 2024-01-23 09:57:57 +01:00
CMakeLists.txt soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00
Kconfig soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00
Kconfig.defconfig soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00
Kconfig.soc soc: xtensa,riscv: esp32xx: refactor folder structure 2023-07-25 18:12:33 +02:00