2dcbb0ee3f
These options are meant to be selected by SoC series supporting (C|P)LIC. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
43 lines
629 B
Plaintext
43 lines
629 B
Plaintext
# Copyright (c) 2023 Meta
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# SPDX-License-Identifier: Apache-2.0
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if SOC_RISCV32_VIRTUAL_RENODE
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config SOC
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default "renode_virt"
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 4000000
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config RISCV_SOC_INTERRUPT_INIT
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default y
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config RISCV_GP
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default y
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config 1ST_LEVEL_INTERRUPT_BITS
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default 4
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config NUM_2ND_LEVEL_AGGREGATORS
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default 2
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config 2ND_LEVEL_INTERRUPT_BITS
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default 11
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config 2ND_LVL_ISR_TBL_OFFSET
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default 12
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config 2ND_LVL_INTR_00_OFFSET
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default 11
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config 2ND_LVL_INTR_01_OFFSET
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default 4
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config MAX_IRQ_PER_AGGREGATOR
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default 1023
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config NUM_IRQS
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default 2058
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endif # SOC_RISCV32_VIRTUAL_RENODE
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