a3a4bf915b
This commit adds the `litex,vexriscv-standard` compatible string. This helps identify the core type from the final devicetree alone. The VexRiscv core version is defined in this repository: https://github.com/litex-hub/zephyr-on-litex-vexriscv. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com> |
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| .. | ||
| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||