6edb0624d8
The exception mask needs to cover MCAUSE bits 11:0, there's no need to overengineer this setting using DT properties. Ref. https://doc.nucleisys.com/nuclei_spec/isa/core_csr.html#mcause Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com>
9 lines
202 B
YAML
9 lines
202 B
YAML
# Copyright (c) 2021 TOKITA Hiroshi <tokita.hiroshi@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: Nuclei Bumblebee RISC-V Core
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compatible: "nuclei,bumblebee"
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include: riscv,cpus.yaml
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