52deadd420
This commit introduces support for querying i.MX93's SAI clocks. Signed-off-by: Laurentiu Mihalcea <laurentiu.mihalcea@nxp.com>
156 lines
3.3 KiB
C
156 lines
3.3 KiB
C
/*
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* Copyright (c) 2021, NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT nxp_imx_ccm_rev2
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#include <errno.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/dt-bindings/clock/imx_ccm_rev2.h>
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#include <fsl_clock.h>
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#define LOG_LEVEL CONFIG_CLOCK_CONTROL_LOG_LEVEL
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(clock_control);
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static int mcux_ccm_on(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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#ifdef CONFIG_ETH_NXP_ENET
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if ((uint32_t)sub_system == IMX_CCM_ENET_CLK) {
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CLOCK_EnableClock(kCLOCK_Enet);
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}
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#endif
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return 0;
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}
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static int mcux_ccm_off(const struct device *dev,
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clock_control_subsys_t sub_system)
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{
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return 0;
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}
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static int mcux_ccm_get_subsys_rate(const struct device *dev,
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clock_control_subsys_t sub_system,
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uint32_t *rate)
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{
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uint32_t clock_name = (size_t) sub_system;
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uint32_t clock_root, peripheral, instance;
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peripheral = (clock_name & IMX_CCM_PERIPHERAL_MASK);
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instance = (clock_name & IMX_CCM_INSTANCE_MASK);
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switch (peripheral) {
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#ifdef CONFIG_I2C_MCUX_LPI2C
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case IMX_CCM_LPI2C1_CLK:
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clock_root = kCLOCK_Root_Lpi2c1 + instance;
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break;
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#endif
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#ifdef CONFIG_SPI_MCUX_LPSPI
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case IMX_CCM_LPSPI1_CLK:
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clock_root = kCLOCK_Root_Lpspi1 + instance;
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break;
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#endif
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#ifdef CONFIG_UART_MCUX_LPUART
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case IMX_CCM_LPUART1_CLK:
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case IMX_CCM_LPUART2_CLK:
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clock_root = kCLOCK_Root_Lpuart1 + instance;
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break;
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#endif
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#if CONFIG_IMX_USDHC
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case IMX_CCM_USDHC1_CLK:
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case IMX_CCM_USDHC2_CLK:
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clock_root = kCLOCK_Root_Usdhc1 + instance;
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break;
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#endif
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#ifdef CONFIG_DMA_MCUX_EDMA
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case IMX_CCM_EDMA_CLK:
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clock_root = kCLOCK_Root_Bus;
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break;
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case IMX_CCM_EDMA_LPSR_CLK:
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clock_root = kCLOCK_Root_Bus_Lpsr;
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break;
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#endif
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#ifdef CONFIG_PWM_MCUX
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case IMX_CCM_PWM_CLK:
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clock_root = kCLOCK_Root_Bus;
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break;
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#endif
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#ifdef CONFIG_CAN_MCUX_FLEXCAN
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case IMX_CCM_CAN1_CLK:
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clock_root = kCLOCK_Root_Can1 + instance;
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break;
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#endif
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#ifdef CONFIG_COUNTER_MCUX_GPT
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case IMX_CCM_GPT_CLK:
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clock_root = kCLOCK_Root_Gpt1 + instance;
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break;
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#endif
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#ifdef CONFIG_I2S_MCUX_SAI
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case IMX_CCM_SAI1_CLK:
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clock_root = kCLOCK_Root_Sai1;
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break;
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case IMX_CCM_SAI2_CLK:
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clock_root = kCLOCK_Root_Sai2;
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break;
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case IMX_CCM_SAI3_CLK:
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clock_root = kCLOCK_Root_Sai3;
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break;
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case IMX_CCM_SAI4_CLK:
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clock_root = kCLOCK_Root_Sai4;
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break;
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#endif
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#ifdef CONFIG_ETH_NXP_ENET
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case IMX_CCM_ENET_CLK:
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clock_root = kCLOCK_Root_Bus;
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break;
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#endif
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#if defined(CONFIG_SOC_MIMX93_A55) && defined(CONFIG_DAI_NXP_SAI)
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case IMX_CCM_SAI1_CLK:
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case IMX_CCM_SAI2_CLK:
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case IMX_CCM_SAI3_CLK:
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clock_root = kCLOCK_Root_Sai1 + instance;
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uint32_t mux = CLOCK_GetRootClockMux(clock_root);
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uint32_t divider = CLOCK_GetRootClockDiv(clock_root);
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/* assumption: SAI's SRC is AUDIO_PLL */
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if (mux != 1) {
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return -EINVAL;
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}
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/* assumption: AUDIO_PLL's frequency is 393216000 Hz */
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*rate = 393216000 / divider;
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return 0;
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#endif
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default:
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return -EINVAL;
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}
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#ifdef CONFIG_SOC_MIMX93_A55
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*rate = CLOCK_GetIpFreq(clock_root);
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#else
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*rate = CLOCK_GetRootClockFreq(clock_root);
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#endif
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return 0;
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}
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static const struct clock_control_driver_api mcux_ccm_driver_api = {
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.on = mcux_ccm_on,
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.off = mcux_ccm_off,
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.get_rate = mcux_ccm_get_subsys_rate,
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};
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DEVICE_DT_INST_DEFINE(0, NULL, NULL, NULL, NULL, PRE_KERNEL_1,
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CONFIG_CLOCK_CONTROL_INIT_PRIORITY,
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&mcux_ccm_driver_api);
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