72aee4b90b
for nucleo_stm32g0b1 board. the HSI48 clock is the clock used by default for the USB controller, however its default tolerance is not enough for the USB specification, leading to some random errors depending on many factors, including the upstream HUB or host. this commit adds an option in the device tree to enable the STM32 Clock recovery system (CRS) using USB SOF packet reception as a reference, which brings the HSI48 within the required accuracy for USB transfers. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net> Signed-off-by: Marc Desvaux <marc.desvaux-ext@st.com>
93 lines
1.8 KiB
C
93 lines
1.8 KiB
C
/*
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*
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* Copyright (c) 2019 Ilya Tagunov
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* Copyright (c) 2019 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_crs.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_utils.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/sys/util.h>
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#include <zephyr/drivers/clock_control/stm32_clock_control.h>
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#include "clock_stm32_ll_common.h"
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#if defined(STM32_PLL_ENABLED)
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/**
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* @brief Return PLL source
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*/
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__unused
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static uint32_t get_pll_source(void)
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{
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/* Configure PLL source */
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return LL_RCC_PLLSOURCE_HSI;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return LL_RCC_PLLSOURCE_HSE;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief get the pll source frequency
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*/
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__unused
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uint32_t get_pllsrc_frequency(void)
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{
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if (IS_ENABLED(STM32_PLL_SRC_HSI)) {
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return STM32_HSI_FREQ;
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} else if (IS_ENABLED(STM32_PLL_SRC_HSE)) {
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return STM32_HSE_FREQ;
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}
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__ASSERT(0, "Invalid source");
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return 0;
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}
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/**
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* @brief Set up pll configuration
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*/
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__unused
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void config_pll_sysclock(void)
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{
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LL_RCC_PLL_ConfigDomain_SYS(get_pll_source(),
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pllm(STM32_PLL_M_DIVISOR),
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STM32_PLL_N_MULTIPLIER,
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pllr(STM32_PLL_R_DIVISOR));
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LL_RCC_PLL_EnableDomain_SYS();
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}
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#endif /* defined(STM32_PLL_ENABLED) */
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/**
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* @brief Activate default clocks
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*/
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void config_enable_default_clocks(void)
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{
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/* Enable the power interface clock */
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
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#if defined(CRS)
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if (IS_ENABLED(STM32_HSI48_CRS_USB_SOF)) {
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LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_CRS);
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/*
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* After reset the CRS configuration register
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* (CRS_CFGR) value corresponds to an USB SOF
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* synchronization. FIXME: write it anyway.
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*/
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LL_CRS_EnableAutoTrimming();
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LL_CRS_EnableFreqErrorCounter();
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}
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#endif /* defined(CRS) */
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}
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