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Filip Kokosinski f80347ec95 dts/riscv/lowrisc: add lowrisc,ibex compatible string 
The OpenTitan Earlgrey SoC has the lowRISC Ibex CPU core. This commits adds
the `lowrisc,ibex` compatible string to reflect that.

Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
2024-01-31 10:41:49 +01:00
..
opentitan_earlgrey.dtsi dts/riscv/lowrisc: add lowrisc,ibex compatible string 2024-01-31 10:41:49 +01:00