c80ace50f4
For more effective code execution on STM32 devices is convenient to enable flash prefetch buffer. To be enabled by default, possible to disable using kconfig. Signed-off-by: Lubos Koudelka <lubos.koudelka@st.com>
61 lines
1.3 KiB
C
61 lines
1.3 KiB
C
/*
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* Copyright (c) 2023 STMicroelectronics
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief System/hardware module for STM32WBA processor
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*/
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#include <zephyr/device.h>
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#include <zephyr/init.h>
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#include <stm32_ll_bus.h>
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#include <stm32_ll_pwr.h>
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#include <stm32_ll_rcc.h>
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#include <stm32_ll_icache.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/irq.h>
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#include <zephyr/logging/log.h>
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#include <cmsis_core.h>
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#define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
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LOG_MODULE_REGISTER(soc);
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/**
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* @brief Perform basic hardware initialization at boot.
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*
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* This needs to be run from the very beginning.
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* So the init priority has to be 0 (zero).
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*
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* @return 0
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*/
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int stm32wba_init(void)
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{
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/* Enable instruction cache in 1-way (direct mapped cache) */
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LL_ICACHE_SetMode(LL_ICACHE_1WAY);
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LL_ICACHE_Enable();
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#ifdef CONFIG_STM32_FLASH_PREFETCH
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__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
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#endif
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/* Update CMSIS SystemCoreClock variable (HCLK) */
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/* At reset, system core clock is set to 16 MHz from HSI */
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SystemCoreClock = 16000000;
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/* Enable PWR */
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LL_AHB4_GRP1_EnableClock(LL_AHB4_GRP1_PERIPH_PWR);
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#if defined(CONFIG_POWER_SUPPLY_DIRECT_SMPS)
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LL_PWR_SetRegulatorSupply(LL_PWR_SMPS_SUPPLY);
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#elif defined(CONFIG_POWER_SUPPLY_LDO)
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LL_PWR_SetRegulatorSupply(LL_PWR_LDO_SUPPLY);
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#endif
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return 0;
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}
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SYS_INIT(stm32wba_init, PRE_KERNEL_1, 0);
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