Rajavardhan Gundi dadf9e7a81 xtensa: intel_s1000: implement interrupt mechanism ... intel_s1000 has multiple levels of interrupts consisting of core, CAVS Logic and designware interrupt controller. This patchset modifies the regular gen_isr mechanism to support these multiple levels. Change-Id: I0450666d4e601dfbc8cadc9c9d8100afb61a214c Signed-off-by: Rajavardhan Gundi <rajavardhan.gundi@intel.com> Signed-off-by: Anas Nashif <anas.nashif@intel.com>		2018-05-01 16:46:41 -04:00
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arc	arch: arc: add the support of STACK_SENTINEL	2018-04-17 10:50:12 -07:00
arm	arch/arm/soc/st_stm32: Fix typos in soc.h	2018-04-28 20:46:08 +05:30
common	drivers/interrupt_controller: Introduce multi-level interrupt support	2018-02-06 22:39:05 -05:00
nios2	cleanup: replace old jira numbers with GH issues	2018-03-26 13:13:04 -04:00
posix	kernel: Further unify _reschedule APIs	2018-04-24 03:57:20 +05:30
riscv32	arch: riscv32: fe310: Always-On domain adress definition	2018-04-05 08:08:08 -05:00
x86	x86: minnowboard: Enable the userspace mode	2018-04-25 14:46:00 -07:00
xtensa	xtensa: intel_s1000: implement interrupt mechanism	2018-05-01 16:46:41 -04:00
CMakeLists.txt	Introduce cmake-based rewrite of KBuild	2017-11-08 20:00:22 -05:00
Kconfig	kconfig: fix menuconfig	2018-04-30 09:22:48 -07:00