13484b5bdc
UART CLK does not support the 48MHz frequency option Signed-off-by: Richard Wheatley <richard.wheatley@ambiq.com>
73 lines
2.2 KiB
C
73 lines
2.2 KiB
C
/*
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* Copyright (c) 2023 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_
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#define ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_
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#include <zephyr/device.h>
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#include <zephyr/kernel.h>
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#include "uart_pl011_registers.h"
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#define PWRCTRL_MAX_WAIT_US 5
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static inline void pl011_ambiq_enable_clk(const struct device *dev)
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{
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get_uart(dev)->cr |= PL011_CR_AMBIQ_CLKEN;
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}
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static inline int pl011_ambiq_clk_set(const struct device *dev, uint32_t clk)
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{
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uint8_t clksel;
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switch (clk) {
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case 3000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_3MHZ;
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break;
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case 6000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_6MHZ;
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break;
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case 12000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_12MHZ;
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break;
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case 24000000:
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clksel = PL011_CR_AMBIQ_CLKSEL_24MHZ;
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break;
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default:
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return -EINVAL;
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}
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get_uart(dev)->cr |= FIELD_PREP(PL011_CR_AMBIQ_CLKSEL, clksel);
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return 0;
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}
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static inline int clk_enable_ambiq_uart(const struct device *dev, uint32_t clk)
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{
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pl011_ambiq_enable_clk(dev);
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return pl011_ambiq_clk_set(dev, clk);
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}
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/* Problem: writes to pwrcfg reg take at most PWCTRL_MAX_WAIT_US time to propagate.
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* Solution: busy wait for PWCTRL_MAX_WAIT_US microseconds to ensure that register
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* writes have propagated.
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*/
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#define QUIRK_AMBIQ_UART_DEFINE(n) \
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static int pwr_on_ambiq_uart_##n(void) \
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{ \
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uint32_t addr = DT_REG_ADDR(DT_INST_PHANDLE(n, ambiq_pwrcfg)) + \
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DT_INST_PHA(n, ambiq_pwrcfg, offset); \
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sys_write32((sys_read32(addr) | DT_INST_PHA(n, ambiq_pwrcfg, mask)), addr); \
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k_busy_wait(PWRCTRL_MAX_WAIT_US); \
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return 0; \
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}
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#define PL011_QUIRK_AMBIQ_UART_DEFINE(n) \
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COND_CODE_1(DT_NODE_HAS_COMPAT(DT_DRV_INST(n), ambiq_uart), (QUIRK_AMBIQ_UART_DEFINE(n)), \
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())
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#endif /* ZEPHYR_DRIVERS_SERIAL_UART_PL011_AMBIQ_H_ */
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