d0fe965b9f
Microchip MEC172x has a modified eSPI SAF hardware implementation. Hardware changes include multiple clock dividers for each SPI flash device and data transfer using QMSPI local DMA. espi reset interrupt is made a higer priority in MEC172x devicetree because espi reset event resets all espi hardware and we don't to want to service any other espi interrupt blocks when espi reset occurs. Signed-off-by: Jay Vasanth <jay.vasanth@microchip.com>
15 lines
723 B
CMake
15 lines
723 B
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_ESPI_XEC espi_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_NPCX espi_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_NPCX host_subs_npcx.c)
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zephyr_library_sources_ifdef(CONFIG_USERSPACE espi_handlers.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_EMUL espi_emul.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_SAF_XEC espi_saf_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_XEC_V2 espi_mchp_xec_v2.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_XEC_V2 espi_mchp_xec_host_v2.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_IT8XXX2 espi_it8xxx2.c)
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zephyr_library_sources_ifdef(CONFIG_ESPI_SAF_XEC_V2 espi_saf_mchp_xec_v2.c)
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