2e04bfdfe0
Changes to code:
1. Renamed CAVS_IPC API from common/include/cavs_ipc.h to
common/include/intel_adsp_ipc.h. Renamed all API functions and structs -
added "intel_adsp_" prefix.
2. Moved definitions from intel-ipc-regs.h and ace-ipc-regs.g to SOC
specific headers include/<soc_name>/adsp_ipc_regs.h.
3. Added new common intel_adsp_ipc_devtree.h header with new
macros to retrieve IPC and IDC nodes and register addresses.
Put those new macros in code replacing hardcoded values outside of
devicetree.
4. Changed documentation of IDC and renamed IDC register struct
to have common name between all intel adsp socs.
5. Removed excessive docs description on cAVS IPC protocol.
Changes to Devicetree:
1. Renamed in all CAVS boards .dtsi files content in IPC nodes:
- "cavs_host_ipc" node labels to "adsp_ipc" labels.
- compatible "intel,cavs-host-ipc" renamed to
"intel,adsp-host-ipc".
2. Added (previously missing) yaml file for "intel,adsp-host-ipc"
compatible.
3. Renamed in all CAVS boards .dtsi files content in IDC nodes:
- "idc" node labels to "adsp_idc" labels.
- compatible "intel,cavs-idc" renamed to "intel-adsp-idc"
4. Renamed intel,cavs_idc.yaml file to intel,adsp_idc.yaml
so it is suitable for both CAVS and ACE SoC family.
Moved it from ipm bindings to ipc bindings where it belongs.
Changes to Kconfig:
1. Renamed existing Kconfig option CONFIG_CAVS_IPC to
INTEL_ADSP_IPC.
2. For renamed INTEL_ADSP_IPC addded default value based on
status of the "adsp-ipc" and "adsp-ipc" node.
Signed-off-by: Andrey Borisovich <andrey.borisovich@intel.com>
69 lines
2.1 KiB
C
69 lines
2.1 KiB
C
/*
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* Copyright (c) 2020 Intel Corporation
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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#define ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_
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#define DT_DRV_COMPAT intel_adsp_idc
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#include <intel_adsp_ipc_devtree.h>
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/* Redeclaration of the earlier IDC register API for platforms being
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* held back on this driver.
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*/
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# ifndef IPC_DSP_BASE
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# define IPC_DSP_BASE(core) (INTEL_ADSP_IDC_REG_ADDRESS + 0x80 * (core))
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# endif
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#define IPC_IDCTFC(x) (x * 0x10)
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#define IPC_IDCTFC_BUSY BIT(31)
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#define IPC_IDCTFC_MSG_MASK 0x7FFFFFFF
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#define IPC_IDCTEFC(x) (0x4 + x * 0x10)
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#define IPC_IDCTEFC_MSG_MASK 0x3FFFFFFF
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#define IPC_IDCITC(x) (0x8 + x * 0x10)
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#define IPC_IDCITC_MSG_MASK 0x7FFFFFFF
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#define IPC_IDCITC_BUSY BIT(31)
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#define IPC_IDCIETC(x) (0xc + x * 0x10)
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#define IPC_IDCIETC_MSG_MASK 0x3FFFFFFF
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#define IPC_IDCIETC_DONE BIT(30)
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#define IPC_IDCCTL 0x50
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#define IPC_IDCCTL_IDCTBIE(x) BIT(x)
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#define IPM_CAVS_IDC_ID_MASK \
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(CAVS_IDC_TYPE(CAVS_IDC_TYPE_MASK) | \
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CAVS_IDC_HEADER(CAVS_IDC_HEADER_MASK))
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/* IDC message type. */
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#define CAVS_IDC_TYPE_SHIFT 24U
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#define CAVS_IDC_TYPE_MASK 0x7FU
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#define CAVS_IDC_TYPE(x) \
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(((x) & CAVS_IDC_TYPE_MASK) << CAVS_IDC_TYPE_SHIFT)
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/* IDC message header. */
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#define CAVS_IDC_HEADER_MASK 0xFFFFFFU
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#define CAVS_IDC_HEADER(x) ((x) & CAVS_IDC_HEADER_MASK)
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/* IDC message extension. */
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#define CAVS_IDC_EXTENSION_MASK 0x3FFFFFFFU
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#define CAVS_IDC_EXTENSION(x) ((x) & CAVS_IDC_EXTENSION_MASK)
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/* Scheduler IPI message (type 0x7F, header 'IPI' in ascii) */
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_DATA 0
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#define IPM_CAVS_IDC_MSG_SCHED_IPI_ID \
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(CAVS_IDC_TYPE(0x7FU) | CAVS_IDC_HEADER(0x495049U))
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static inline uint32_t idc_read(uint32_t reg, uint32_t core_id)
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{
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return *((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg));
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}
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static inline void idc_write(uint32_t reg, uint32_t core_id, uint32_t val)
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{
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*((volatile uint32_t*)(IPC_DSP_BASE(core_id) + reg)) = val;
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}
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int cavs_idc_smp_init(const struct device *dev);
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#endif /* ZEPHYR_DRIVERS_IPM_IPM_CAVS_IDC_H_ */
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