b823bacecb
Add a new nodes for PPR's VEVIF. In app cores, VEVIF registers are part of the VPR peripheral, so it is exposed as a child node (since it requires its own properties, eg #mbox-cells). In VPR, it's a CPU child since it's not a memory-mapped peripheral, but used with CSRs. Signed-off-by: Gerard Marull-Paretas <gerard@teslabs.com> |
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| .. | ||
| arc/synopsys | ||
| arm | ||
| arm64 | ||
| bindings | ||
| common | ||
| nios2/intel | ||
| posix | ||
| riscv | ||
| sparc/gaisler | ||
| x86/intel | ||
| xtensa | ||
| binding-template.yaml | ||
| Kconfig | ||