zephyr/boards/nxp/frdm_k64f/frdm_k64f-pinctrl.dtsi
Declan Snyder 537d5c310c dts: nxp: Convert ENET DT default to new binding.
Convert all of the NXP SOCs with ENET to use the new
binding scheme, which is used by the new driver.

Convert any boards using this SOC to the new scheme as well,
and remove from the documentation the bit about the experimental
nature of the new driver and the overlay that shall no longer exist.

Some of the boards I do not have the hardware of, so apologies
if something breaks, as I have no way to know. All the boards
were made sure to at least build.

Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
2024-04-18 11:18:31 +02:00

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/*
* NOTE: Autogenerated file by gen_board_pinctrl.py
* for MK64FN1M0VLL12/signal_configuration.xml
*
* Copyright (c) 2022, NXP
* SPDX-License-Identifier: Apache-2.0
*/
#include <nxp/kinetis/MK64FN1M0VLL12-pinctrl.h>
&pinctrl {
adc0_default: adc0_default {
group0 {
pinmux = <ADC0_SE14_PTC0>;
drive-strength = "low";
slew-rate = "fast";
};
};
adc1_default: adc1_default {
group0 {
pinmux = <ADC1_SE14_PTB10>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_enet: pinmux_enet {
group1 {
pinmux = <RMII0_RXER_PTA5>,
<RMII0_RXD1_PTA12>,
<RMII0_RXD0_PTA13>,
<RMII0_CRS_DV_PTA14>,
<RMII0_TXEN_PTA15>,
<RMII0_TXD0_PTA16>,
<RMII0_TXD1_PTA17>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_enet_mdio: pinmux_enet_mdio {
group0 {
pinmux = <RMII0_MDIO_PTB0>;
drive-strength = "low";
drive-open-drain;
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <RMII0_MDC_PTB1>;
drive-strength = "low";
slew-rate = "fast";
};
};
pinmux_ptp: pinmux_ptp {
group0 {
pinmux = <ENET0_1588_TMR0_PTC16>,
<ENET0_1588_TMR1_PTC17>,
<ENET0_1588_TMR2_PTC18>;
drive-strength = "low";
slew-rate = "fast";
};
};
flexcan0_default: flexcan0_default {
group0 {
pinmux = <CAN0_RX_PTB19>;
drive-strength = "low";
bias-pull-up;
slew-rate = "fast";
};
group1 {
pinmux = <CAN0_TX_PTB18>;
drive-strength = "low";
slew-rate = "fast";
};
};
ftm0_default: ftm0_default {
group0 {
pinmux = <FTM0_CH0_PTC1>;
drive-strength = "low";
slew-rate = "fast";
};
};
ftm3_default: ftm3_default {
group0 {
pinmux = <FTM3_CH4_PTC8>,
<FTM3_CH5_PTC9>;
drive-strength = "low";
slew-rate = "fast";
};
};
i2c0_default: i2c0_default {
group0 {
pinmux = <I2C0_SCL_PTE24>,
<I2C0_SDA_PTE25>;
drive-strength = "low";
drive-open-drain;
slew-rate = "fast";
};
};
/* PTC16 and PTC17 conflict with uart3 pins */
ptp_default: ptp_default {
group0 {
pinmux = <ENET0_1588_TMR0_PTC16>,
<ENET0_1588_TMR1_PTC17>,
<ENET0_1588_TMR2_PTC18>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* pins conflict with uart2 */
spi0_default: spi0_default {
group0 {
pinmux = <SPI0_PCS0_PTD0>,
<SPI0_SCK_PTD1>,
<SPI0_SOUT_PTD2>,
<SPI0_SIN_PTD3>;
drive-strength = "low";
slew-rate = "fast";
};
};
spi1_default: spi1_default {
group0 {
pinmux = <SPI1_PCS0_PTE4>,
<SPI1_SCK_PTE2>,
<SPI1_SOUT_PTE3>,
<SPI1_SIN_PTE1>;
drive-strength = "low";
slew-rate = "fast";
};
};
uart0_default: uart0_default {
group0 {
pinmux = <UART0_RX_PTB16>,
<UART0_TX_PTB17>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* pins conflict with spi0 */
uart2_default: uart2_default {
group0 {
pinmux = <UART2_CTS_b_PTD1>,
<UART2_RTS_b_PTD0>,
<UART2_RX_PTD2>,
<UART2_TX_PTD3>;
drive-strength = "low";
slew-rate = "fast";
};
};
/* PTC16 and PTC17 conflict with PTP timer pins */
uart3_default: uart3_default {
group0 {
pinmux = <UART3_RX_PTC16>,
<UART3_TX_PTC17>;
drive-strength = "low";
slew-rate = "fast";
};
};
};