537d5c310c
Convert all of the NXP SOCs with ENET to use the new binding scheme, which is used by the new driver. Convert any boards using this SOC to the new scheme as well, and remove from the documentation the bit about the experimental nature of the new driver and the overlay that shall no longer exist. Some of the boards I do not have the hardware of, so apologies if something breaks, as I have no way to know. All the boards were made sure to at least build. Signed-off-by: Declan Snyder <declan.snyder@nxp.com>
176 lines
3.1 KiB
Plaintext
176 lines
3.1 KiB
Plaintext
/*
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* NOTE: Autogenerated file by gen_board_pinctrl.py
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* for MK64FN1M0VLL12/signal_configuration.xml
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*
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* Copyright (c) 2022, NXP
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <nxp/kinetis/MK64FN1M0VLL12-pinctrl.h>
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&pinctrl {
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adc0_default: adc0_default {
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group0 {
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pinmux = <ADC0_SE14_PTC0>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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adc1_default: adc1_default {
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group0 {
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pinmux = <ADC1_SE14_PTB10>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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pinmux_enet: pinmux_enet {
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group1 {
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pinmux = <RMII0_RXER_PTA5>,
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<RMII0_RXD1_PTA12>,
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<RMII0_RXD0_PTA13>,
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<RMII0_CRS_DV_PTA14>,
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<RMII0_TXEN_PTA15>,
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<RMII0_TXD0_PTA16>,
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<RMII0_TXD1_PTA17>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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pinmux_enet_mdio: pinmux_enet_mdio {
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group0 {
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pinmux = <RMII0_MDIO_PTB0>;
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drive-strength = "low";
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drive-open-drain;
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bias-pull-up;
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slew-rate = "fast";
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};
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group1 {
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pinmux = <RMII0_MDC_PTB1>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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pinmux_ptp: pinmux_ptp {
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group0 {
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pinmux = <ENET0_1588_TMR0_PTC16>,
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<ENET0_1588_TMR1_PTC17>,
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<ENET0_1588_TMR2_PTC18>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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flexcan0_default: flexcan0_default {
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group0 {
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pinmux = <CAN0_RX_PTB19>;
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drive-strength = "low";
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bias-pull-up;
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slew-rate = "fast";
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};
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group1 {
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pinmux = <CAN0_TX_PTB18>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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ftm0_default: ftm0_default {
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group0 {
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pinmux = <FTM0_CH0_PTC1>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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ftm3_default: ftm3_default {
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group0 {
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pinmux = <FTM3_CH4_PTC8>,
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<FTM3_CH5_PTC9>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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i2c0_default: i2c0_default {
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group0 {
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pinmux = <I2C0_SCL_PTE24>,
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<I2C0_SDA_PTE25>;
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drive-strength = "low";
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drive-open-drain;
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slew-rate = "fast";
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};
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};
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/* PTC16 and PTC17 conflict with uart3 pins */
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ptp_default: ptp_default {
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group0 {
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pinmux = <ENET0_1588_TMR0_PTC16>,
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<ENET0_1588_TMR1_PTC17>,
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<ENET0_1588_TMR2_PTC18>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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/* pins conflict with uart2 */
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spi0_default: spi0_default {
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group0 {
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pinmux = <SPI0_PCS0_PTD0>,
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<SPI0_SCK_PTD1>,
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<SPI0_SOUT_PTD2>,
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<SPI0_SIN_PTD3>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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spi1_default: spi1_default {
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group0 {
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pinmux = <SPI1_PCS0_PTE4>,
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<SPI1_SCK_PTE2>,
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<SPI1_SOUT_PTE3>,
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<SPI1_SIN_PTE1>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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uart0_default: uart0_default {
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group0 {
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pinmux = <UART0_RX_PTB16>,
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<UART0_TX_PTB17>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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/* pins conflict with spi0 */
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uart2_default: uart2_default {
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group0 {
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pinmux = <UART2_CTS_b_PTD1>,
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<UART2_RTS_b_PTD0>,
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<UART2_RX_PTD2>,
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<UART2_TX_PTD3>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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/* PTC16 and PTC17 conflict with PTP timer pins */
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uart3_default: uart3_default {
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group0 {
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pinmux = <UART3_RX_PTC16>,
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<UART3_TX_PTC17>;
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drive-strength = "low";
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slew-rate = "fast";
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};
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};
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};
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