a24f0f0b1d
This Ambiq gpio binding provides the GPIO pin mapping for GPIO child nodes tosolve the limitation of the maximum 32 pins handling in GPIO driver API. The gpio-bank nodes can be created under the gpio parent node. Signed-off-by: Aaron Ye <aye@ambiq.com>
85 lines
2.7 KiB
YAML
85 lines
2.7 KiB
YAML
# Copyright (c) 2023 Ambiq Micro Inc. <www.ambiq.com>
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# SPDX-License-Identifier: Apache-2.0
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description: |
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Ambiq GPIO provides the GPIO pin mapping for GPIO child nodes.
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The Ambiq Apollo4x soc designs a single GPIO port with 128 pins.
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It uses 128 continuous 32-bit registers to configure the GPIO pins.
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This binding provides a pin mapping to solve the limitation of the maximum
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32 pins handling in GPIO driver API.
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The Ambiq Apollo4x soc should define one "ambiq,gpio" parent node in soc
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devicetree and some child nodes which are compatible with "ambiq,gpio-bank"
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under this parent node.
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Here is an example of how a "ambiq,gpio" node can be used with the combined
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gpio child nodes:
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gpio: gpio@40010000 {
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compatible = "ambiq,gpio";
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gpio-map-mask = <0xffffffe0 0xffffffc0>;
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gpio-map-pass-thru = <0x1f 0x3f>;
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gpio-map = <
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0x00 0x0 &gpio0_31 0x0 0x0
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0x20 0x0 &gpio32_63 0x0 0x0
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0x40 0x0 &gpio64_95 0x0 0x0
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0x60 0x0 &gpio96_127 0x0 0x0
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>;
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reg = <0x40010000>;
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#gpio-cells = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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ranges;
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gpio0_31: gpio0_31@0 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0>;
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interrupts = <56 0>;
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status = "disabled";
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};
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gpio32_63: gpio32_63@80 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x80>;
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interrupts = <57 0>;
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status = "disabled";
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};
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gpio64_95: gpio64_95@100 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x100>;
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interrupts = <58 0>;
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status = "disabled";
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};
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gpio96_127: gpio96_127@180 {
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compatible = "ambiq,gpio-bank";
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gpio-controller;
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#gpio-cells = <2>;
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reg = <0x180>;
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interrupts = <59 0>;
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status = "disabled";
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};
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};
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In the above example, the gpio@40010000 is a "ambiq,gpio" parent node which
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provides the base register address 0x40010000. It has four "ambiq,gpio-bank"
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child nodes. Each of them covers 32 pins (the default value of "ngpios"
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property is 32). The "reg" property of child nodes defines the register
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address offset. The register address of pin described in gpio-cells can be
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obtained by: base address + child address offset + (pin << 2). For example:
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the address of pin 20 of gpio32_63@80 node is (0x40010000 + 0x80 + (20 << 2))
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= 0x400100D0 and the real GPIO pin number of this pin in soc is (20 + 32)
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= 52.
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compatible: "ambiq,gpio"
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include: [gpio-nexus.yaml, base.yaml]
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