c7d526be04
The only remaining port operations have dedicated API function table entries. Remove the defines for access op (mode), and remove support for access op from all implementations. Signed-off-by: Peter Bigot <peter.bigot@nordicsemi.no>
385 lines
9.3 KiB
C
385 lines
9.3 KiB
C
/*
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* Copyright (c) 2017 Google LLC.
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* Copyright (c) 2019 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <errno.h>
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#include <device.h>
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#include <drivers/gpio.h>
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#include <soc.h>
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#include <drivers/interrupt_controller/sam0_eic.h>
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#include "gpio_utils.h"
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#ifndef PORT_PMUX_PMUXE_A_Val
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#define PORT_PMUX_PMUXE_A_Val (0)
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#endif
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struct gpio_sam0_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config common;
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PortGroup *regs;
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#ifdef CONFIG_SAM0_EIC
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u8_t id;
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#endif
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};
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struct gpio_sam0_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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gpio_port_pins_t debounce;
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#ifdef CONFIG_SAM0_EIC
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sys_slist_t callbacks;
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#endif
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};
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#define DEV_CFG(dev) \
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((const struct gpio_sam0_config *const)(dev)->config->config_info)
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#define DEV_DATA(dev) \
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((struct gpio_sam0_data *const)(dev)->driver_data)
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#ifdef CONFIG_SAM0_EIC
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static void gpio_sam0_isr(u32_t pins, void *arg)
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{
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struct device *const dev = (struct device *) arg;
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struct gpio_sam0_data *const data = DEV_DATA(dev);
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gpio_fire_callbacks(&data->callbacks, dev, pins);
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}
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#endif
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static int gpio_sam0_config(struct device *dev, u32_t pin,
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int flags)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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PortGroup *regs = config->regs;
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PORT_PINCFG_Type pincfg = {
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.reg = 0,
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};
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if ((flags & GPIO_SINGLE_ENDED) != 0) {
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return -ENOTSUP;
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}
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/* Supports disconnected, input, output, or bidirectional */
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if ((flags & GPIO_INPUT) != 0) {
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pincfg.bit.INEN = 1;
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}
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if ((flags & GPIO_OUTPUT) != 0) {
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/* Output is incompatible with pull */
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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return -ENOTSUP;
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}
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/* Bidirectional is supported */
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if ((flags & GPIO_OUTPUT_INIT_LOW) != 0) {
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regs->OUTCLR.reg = BIT(pin);
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} else if ((flags & GPIO_OUTPUT_INIT_HIGH) != 0) {
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regs->OUTSET.reg = BIT(pin);
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}
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regs->DIRSET.reg = BIT(pin);
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} else {
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/* Not output, may be input */
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regs->DIRCLR.reg = BIT(pin);
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/* Pull configuration is supported if not output */
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if ((flags & (GPIO_PULL_UP | GPIO_PULL_DOWN)) != 0) {
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pincfg.bit.PULLEN = 1;
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if ((flags & GPIO_PULL_UP) != 0) {
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regs->OUTSET.reg = BIT(pin);
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} else {
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regs->OUTCLR.reg = BIT(pin);
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}
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}
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}
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/* Preserve debounce flag for interrupt configuration. */
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WRITE_BIT(DEV_DATA(dev)->debounce, pin,
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((flags & GPIO_INT_DEBOUNCE) != 0)
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&& (pincfg.bit.INEN != 0));
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/* Write the now-built pin configuration */
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regs->PINCFG[pin] = pincfg;
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return 0;
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}
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static int gpio_sam0_port_get_raw(struct device *dev,
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gpio_port_value_t *value)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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*value = config->regs->IN.reg;
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return 0;
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}
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static int gpio_sam0_port_set_masked_raw(struct device *dev,
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gpio_port_pins_t mask,
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gpio_port_value_t value)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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u32_t out = config->regs->OUT.reg;
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config->regs->OUT.reg = (out & ~mask) | (value & mask);
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return 0;
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}
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static int gpio_sam0_port_set_bits_raw(struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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config->regs->OUTSET.reg = pins;
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return 0;
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}
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static int gpio_sam0_port_clear_bits_raw(struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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config->regs->OUTCLR.reg = pins;
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return 0;
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}
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static int gpio_sam0_port_toggle_bits(struct device *dev,
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gpio_port_pins_t pins)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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config->regs->OUTTGL.reg = pins;
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return 0;
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}
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#ifdef CONFIG_SAM0_EIC
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static int gpio_sam0_pin_interrupt_configure(struct device *dev,
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unsigned int pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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PortGroup *regs = config->regs;
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PORT_PINCFG_Type pincfg = {
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.reg = regs->PINCFG[pin].reg,
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};
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enum sam0_eic_trigger trigger;
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int rc = 0;
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switch (mode) {
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case GPIO_INT_MODE_DISABLED:
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pincfg.bit.PMUXEN = 0;
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rc = sam0_eic_disable_interrupt(config->id, pin);
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if (rc == -EBUSY) {
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/* Ignore diagnostic disabling disabled */
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rc = 0;
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}
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if (rc == 0) {
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rc = sam0_eic_release(config->id, pin);
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}
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break;
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case GPIO_INT_MODE_LEVEL:
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case GPIO_INT_MODE_EDGE:
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/* Enabling interrupts on a pin requires disconnecting
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* the pin from the I/O pin controller (PORT) module
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* and connecting it to the External Interrupt
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* Controller (EIC). This would prevent using the pin
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* as an output, so interrupts are only supported if
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* the pin is configured as input-only.
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*/
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if ((pincfg.bit.INEN == 0)
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|| ((regs->DIR.reg & BIT(pin)) != 0)) {
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rc = -ENOTSUP;
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break;
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}
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/* Transfer control to EIC */
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pincfg.bit.PMUXEN = 1;
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if ((pin & 1U) != 0) {
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regs->PMUX[pin / 2U].bit.PMUXO = PORT_PMUX_PMUXE_A_Val;
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} else {
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regs->PMUX[pin / 2U].bit.PMUXE = PORT_PMUX_PMUXE_A_Val;
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}
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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trigger = (mode == GPIO_INT_MODE_LEVEL)
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? SAM0_EIC_LOW
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: SAM0_EIC_FALLING;
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break;
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case GPIO_INT_TRIG_HIGH:
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trigger = (mode == GPIO_INT_MODE_LEVEL)
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? SAM0_EIC_HIGH
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: SAM0_EIC_RISING;
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break;
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case GPIO_INT_TRIG_BOTH:
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trigger = SAM0_EIC_BOTH;
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break;
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default:
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rc = -EINVAL;
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break;
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}
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if (rc == 0) {
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rc = sam0_eic_acquire(config->id, pin, trigger,
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(DEV_DATA(dev)->debounce & BIT(pin)) != 0,
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gpio_sam0_isr, dev);
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}
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if (rc == 0) {
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rc = sam0_eic_enable_interrupt(config->id, pin);
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}
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break;
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default:
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rc = -EINVAL;
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break;
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}
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if (rc == 0) {
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/* Update the pin configuration */
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regs->PINCFG[pin] = pincfg;
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}
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return rc;
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}
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static int gpio_sam0_manage_callback(struct device *dev,
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struct gpio_callback *callback, bool set)
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{
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struct gpio_sam0_data *const data = DEV_DATA(dev);
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return gpio_manage_callback(&data->callbacks, callback, set);
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}
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int gpio_sam0_enable_callback(struct device *dev, u32_t pin)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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return sam0_eic_enable_interrupt(config->id, pin);
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}
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int gpio_sam0_disable_callback(struct device *dev, u32_t pin)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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return sam0_eic_disable_interrupt(config->id, pin);
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}
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static u32_t gpio_sam0_get_pending_int(struct device *dev)
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{
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const struct gpio_sam0_config *config = DEV_CFG(dev);
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return sam0_eic_interrupt_pending(config->id);
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}
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#endif
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static const struct gpio_driver_api gpio_sam0_api = {
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.config = gpio_sam0_config,
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.port_get_raw = gpio_sam0_port_get_raw,
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.port_set_masked_raw = gpio_sam0_port_set_masked_raw,
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.port_set_bits_raw = gpio_sam0_port_set_bits_raw,
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.port_clear_bits_raw = gpio_sam0_port_clear_bits_raw,
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.port_toggle_bits = gpio_sam0_port_toggle_bits,
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#ifdef CONFIG_SAM0_EIC
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.pin_interrupt_configure = gpio_sam0_pin_interrupt_configure,
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.manage_callback = gpio_sam0_manage_callback,
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.enable_callback = gpio_sam0_enable_callback,
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.disable_callback = gpio_sam0_disable_callback,
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.get_pending_int = gpio_sam0_get_pending_int,
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#endif
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};
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static int gpio_sam0_init(struct device *dev) { return 0; }
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/* Port A */
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#if DT_ATMEL_SAM0_GPIO_PORT_A_BASE_ADDRESS
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static const struct gpio_sam0_config gpio_sam0_config_0 = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_0_ATMEL_SAM0_GPIO_NGPIOS),
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},
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.regs = (PortGroup *)DT_ATMEL_SAM0_GPIO_PORT_A_BASE_ADDRESS,
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#ifdef CONFIG_SAM0_EIC
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.id = 0,
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#endif
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};
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static struct gpio_sam0_data gpio_sam0_data_0;
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DEVICE_AND_API_INIT(gpio_sam0_0, DT_ATMEL_SAM0_GPIO_PORT_A_LABEL,
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gpio_sam0_init, &gpio_sam0_data_0, &gpio_sam0_config_0,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam0_api);
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#endif
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/* Port B */
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#if DT_ATMEL_SAM0_GPIO_PORT_B_BASE_ADDRESS
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static const struct gpio_sam0_config gpio_sam0_config_1 = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_1_ATMEL_SAM0_GPIO_NGPIOS),
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},
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.regs = (PortGroup *)DT_ATMEL_SAM0_GPIO_PORT_B_BASE_ADDRESS,
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#ifdef CONFIG_SAM0_EIC
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.id = 1,
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#endif
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};
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static struct gpio_sam0_data gpio_sam0_data_1;
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DEVICE_AND_API_INIT(gpio_sam0_1, DT_ATMEL_SAM0_GPIO_PORT_B_LABEL,
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gpio_sam0_init, &gpio_sam0_data_1, &gpio_sam0_config_1,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam0_api);
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#endif
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/* Port C */
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#if DT_ATMEL_SAM0_GPIO_PORT_C_BASE_ADDRESS
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static const struct gpio_sam0_config gpio_sam0_config_2 = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_2_ATMEL_SAM0_GPIO_NGPIOS),
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},
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.regs = (PortGroup *)DT_ATMEL_SAM0_GPIO_PORT_C_BASE_ADDRESS,
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#ifdef CONFIG_SAM0_EIC
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.id = 2,
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#endif
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};
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static struct gpio_sam0_data gpio_sam0_data_2;
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DEVICE_AND_API_INIT(gpio_sam0_2, DT_ATMEL_SAM0_GPIO_PORT_C_LABEL,
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gpio_sam0_init, &gpio_sam0_data_2, &gpio_sam0_config_2,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam0_api);
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#endif
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/* Port D */
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#if DT_ATMEL_SAM0_GPIO_PORT_D_BASE_ADDRESS
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static const struct gpio_sam0_config gpio_sam0_config_3 = {
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.common = {
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_NGPIOS(DT_INST_3_ATMEL_SAM0_GPIO_NGPIOS),
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},
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.regs = (PortGroup *)DT_ATMEL_SAM0_GPIO_PORT_D_BASE_ADDRESS,
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#ifdef CONFIG_SAM0_EIC
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.id = 3,
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#endif
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};
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static struct gpio_sam0_data gpio_sam0_data_3;
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DEVICE_AND_API_INIT(gpio_sam0_3, DT_ATMEL_SAM0_GPIO_PORT_D_LABEL,
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gpio_sam0_init, &gpio_sam0_data_3, &gpio_sam0_config_3,
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POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEVICE,
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&gpio_sam0_api);
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#endif
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