d6f8e9ae5b
This driver exposes STM32 RCC reset functionality through reset API. Information about RCC register offset and bit is encoded just like GD32. The first 5 least significant bits contains register bit number. Next 12 bits are used to keep RCC register offset. Remaining bits are unused. Signed-off-by: Patryk Duda <pdk@semihalf.com>
8 lines
316 B
CMake
8 lines
316 B
CMake
# SPDX-License-Identifier: Apache-2.0
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zephyr_library()
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zephyr_library_sources_ifdef(CONFIG_RESET_GD32 reset_gd32.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_RPI_PICO reset_rpi_pico.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_AST10X0 reset_ast10x0.c)
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zephyr_library_sources_ifdef(CONFIG_RESET_STM32 reset_stm32.c)
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