6a12fb20ab
This commit adds support for tickless operation on the MIPS CP0 timer. The code closely follows the Xtensa and RISCV timer drivers. All tests pass. Signed-off-by: Remy Luisant <remy@luisant.ca> Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
132 lines
2.9 KiB
C
132 lines
2.9 KiB
C
/*
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* Copyright (c) 2020, 2021 Antony Pavlov <antonynpavlov@gmail.com>
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* Copyright (c) 2021 Remy Luisant <remy@luisant.ca>
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*
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* Based on riscv_machine_timer.c and xtensa_sys_timer.c
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <drivers/timer/system_timer.h>
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#include <sys_clock.h>
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#include <spinlock.h>
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#include <soc.h>
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#include <mips/mipsregs.h>
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#define CYC_PER_TICK ((uint32_t)((uint64_t)sys_clock_hw_cycles_per_sec() \
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/ (uint64_t)CONFIG_SYS_CLOCK_TICKS_PER_SEC))
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#define MAX_CYC INT_MAX
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#define MAX_TICKS ((MAX_CYC - CYC_PER_TICK) / CYC_PER_TICK)
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#define MIN_DELAY 1000
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#define TICKLESS IS_ENABLED(CONFIG_TICKLESS_KERNEL)
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static struct k_spinlock lock;
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static uint32_t last_count;
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static ALWAYS_INLINE void set_cp0_compare(uint32_t time)
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{
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_mips_write_32bit_c0_register(CP0_COMPARE, time);
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}
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static ALWAYS_INLINE uint32_t get_cp0_count(void)
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{
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return _mips_read_32bit_c0_register(CP0_COUNT);
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}
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static void timer_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t now = get_cp0_count();
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uint32_t dticks = ((now - last_count) / CYC_PER_TICK);
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last_count = now;
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if (!TICKLESS) {
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uint32_t next = last_count + CYC_PER_TICK;
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if (next - now < MIN_DELAY) {
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next += CYC_PER_TICK;
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}
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set_cp0_compare(next);
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}
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k_spin_unlock(&lock, key);
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sys_clock_announce(TICKLESS ? dticks : 1);
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}
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void sys_clock_set_timeout(int32_t ticks, bool idle)
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{
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ARG_UNUSED(idle);
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if (!TICKLESS) {
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return;
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}
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ticks = ticks == K_TICKS_FOREVER ? MAX_TICKS : ticks;
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ticks = CLAMP(ticks - 1, 0, (int32_t)MAX_TICKS);
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t current_count = get_cp0_count();
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uint32_t delay_wanted = ticks * CYC_PER_TICK;
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/* Round up to next tick boundary. */
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uint32_t adj = (current_count - last_count) + (CYC_PER_TICK - 1);
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if (delay_wanted <= MAX_CYC - adj) {
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delay_wanted += adj;
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} else {
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delay_wanted = MAX_CYC;
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}
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delay_wanted = (delay_wanted / CYC_PER_TICK) * CYC_PER_TICK;
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if ((int32_t)(delay_wanted + last_count - current_count) < MIN_DELAY) {
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delay_wanted += CYC_PER_TICK;
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}
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set_cp0_compare(delay_wanted + last_count);
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k_spin_unlock(&lock, key);
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}
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uint32_t sys_clock_elapsed(void)
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{
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if (!TICKLESS) {
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return 0;
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}
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k_spinlock_key_t key = k_spin_lock(&lock);
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uint32_t ticks_elapsed = (get_cp0_count() - last_count) / CYC_PER_TICK;
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k_spin_unlock(&lock, key);
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return ticks_elapsed;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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return get_cp0_count();
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}
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static int sys_clock_driver_init(const struct device *dev)
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{
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ARG_UNUSED(dev);
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IRQ_CONNECT(MIPS_MACHINE_TIMER_IRQ, 0, timer_isr, NULL, 0);
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last_count = get_cp0_count();
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/*
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* In a tickless system the first tick might possibly be pushed
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* much further into the future than is being done here.
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*/
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set_cp0_compare(last_count + CYC_PER_TICK);
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irq_enable(MIPS_MACHINE_TIMER_IRQ);
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return 0;
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}
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SYS_INIT(sys_clock_driver_init, PRE_KERNEL_2,
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CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);
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