c592690649
This commit moves the bindings of RISC-V cores from `dts/bindings/riscv` to `dts/bindings/cpu`. This change aligns the bindings of RISC-V cores with other architectures. Signed-off-by: Filip Kokosinski <fkokosinski@antmicro.com>
9 lines
200 B
YAML
9 lines
200 B
YAML
# Copyright (c) 2021 Gerson Fernando Budke <nandojve@gmail.com>
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# SPDX-License-Identifier: Apache-2.0
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description: SiFive E24 Standard Core CPU
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compatible: "sifive,e24"
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include: sifive-common.yaml
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