Harshit Agarwal ccb2a0df04 dts: riscv: add PolarFire SoC system controller QSPI interface ... Add support for Microchip's PolarFire SoC system controller QSPI interface. Signed-off-by: Harshit Agarwal <harshit.agarwal@microchip.com>		2024-02-01 04:33:16 -05:00
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arc/synopsys	drivers: spi: dw: define max-xfer-size	2024-01-20 13:11:42 +01:00
arm	dts: bindings: arm: nordic,nrf-ficr: add #nordic,ficr-cells	2024-01-31 13:40:59 +00:00
arm64	dts: arm64: intel: dtsi support for cadence Nand driver for Agilex5	2024-01-30 18:01:31 +01:00
bindings	drivers: display: ili9xxx: convert to MIPI DBI API	2024-01-31 16:01:45 +00:00
common	dts/arm: stm32: Add clocks nodes on stm32wb,l4 and stm32f4 series	2021-04-27 11:53:37 +02:00
nios2/intel	dts: nios2: intel: nios2-qemu: add jtag interrupt	2023-01-27 14:24:43 -05:00
posix	dts: posix: Add DTS support for POSIX architecture	2019-05-28 21:14:19 -04:00
riscv	dts: riscv: add PolarFire SoC system controller QSPI interface	2024-02-01 04:33:16 -05:00
sparc/gaisler	dts/sparc/gaisler: add SoC and board compatible strings	2023-05-02 10:53:27 +02:00
x86/intel	boards: x86: add pci controller node with acpi pnp id	2024-01-31 15:03:06 +01:00
xtensa	soc: esp32: refactor esp32_net	2024-01-13 00:22:24 +00:00
binding-template.yaml	doc: devicetree: overhaul bindings guide	2021-04-22 15:32:10 +02:00
Kconfig	dts: drop HAS_DTS	2023-10-20 12:18:17 -07:00