Alexander Razinkov d2c101d466 kernel: init: conditional .bss section zeroing ... Some platforms already have .bss section zeroed-out externally before the Zephyr initialization and there is no sence to zero it out the second time from the SW. Such boot-time optimization could be critical e.g. for RTL Simulation. Signed-off-by: Alexander Razinkov <alexander.razinkov@syntacore.com>		2023-11-08 10:07:26 +01:00
..
arc	arch: remove wait_q.h include	2023-09-12 12:55:36 -04:00
arm	arch: cortex_ar: Introduce SMP support into Cortex-A/R aarch32	2023-11-06 15:32:01 -06:00
arm64	arch: arm64: Re-init HCR_EL2 in z_arm64_el2_init	2023-11-06 10:14:20 +01:00
common	irq: relocate multi-level irq out of irq.h	2023-10-30 11:43:39 -04:00
mips	COVERAGE: Fix COVERAGE_GCOV dependencies	2023-08-24 15:36:31 +02:00
nios2	arch: nios2: Remove unused absolute symbols	2023-04-18 10:51:28 -04:00
posix	include: always use <> for Zephyr includes	2023-09-14 13:49:58 +02:00
riscv	irq: relocate multi-level irq out of irq.h	2023-10-30 11:43:39 -04:00
sparc	SPARC: Update the Flush windows software trap	2023-10-25 09:54:31 -05:00
x86	arch: x86: Use ACPICA typdef instead of struct name	2023-11-06 12:32:31 +01:00
xtensa	xtensa: add custom mem range check functions	2023-10-20 15:08:34 +02:00
CMakeLists.txt	cmake: enable -Wshadow partially for in-tree code	2023-08-22 11:39:58 +02:00
Kconfig	kernel: init: conditional .bss section zeroing	2023-11-08 10:07:26 +01:00