Jordan Yates d8f186aa4a arch: common: semihost: add semihosting operations ... Add an API that utilizes the ARM semihosting mechanism to interact with the host system when a device is being emulated or run under a debugger. RISCV is implemented in terms of the ARM implementation, and therefore the ARM definitions cross enough architectures to be defined 'common'. Functionality is exposed as a separate API instead of syscall implementations (`_lseek`, `_open`, etc) due to various quirks with the ARM mechanisms that means function arguments are not standard. For more information see: https://developer.arm.com/documentation/dui0471/m/what-is-semihosting- Signed-off-by: Jordan Yates <jordan.yates@data61.csiro.au> impl		2022-04-21 13:04:52 +02:00
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core	arch: common: semihost: add semihosting operations	2022-04-21 13:04:52 +02:00
include	riscv: implement arch_switch()	2022-03-21 07:28:05 -04:00
CMakeLists.txt	riscv: toolchain arguments for a 64-bit build	2019-08-09 09:11:45 -05:00
Kconfig	arch/riscv: Adding KConfig options for 'A' and 'M' RISC-V extensions	2022-03-22 18:00:32 -04:00