70f5411074
Set the PLL1_Q divider to 6 give a can core clock of 80MHz to resolve fdcan_clk reception problem because M_CAN requires that the host clock "APB1" should be higher or equal to the CAN core clock "PLL1_Q". Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <marwa.ibenelhadjmessaoud-ext@st.com> |
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| .. | ||
| doc | ||
| arduino_r3_connector.dtsi | ||
| board.cmake | ||
| board.yml | ||
| Kconfig.defconfig | ||
| Kconfig.stm32h573i_dk | ||
| stm32h573i_dk.dts | ||
| stm32h573i_dk.yaml | ||
| stm32h573i_dk_defconfig | ||