e08d07c97d
Some arches may want to define this as an inline function, or define in core arch code instead of timer driver code. Unfortunately, this means we need to remove from the footprint tests, but this is not typically a large function. Issue: ZEP-1546 Change-Id: Ic0d7a33507da855995838f4703d872cd613a2ca2 Signed-off-by: Andrew Boie <andrew.p.boie@intel.com>
99 lines
2.4 KiB
C
99 lines
2.4 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <kernel.h>
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#include <arch/cpu.h>
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#include <device.h>
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#include <system_timer.h>
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#include <board.h>
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typedef struct {
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uint32_t val_low;
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uint32_t val_high;
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} riscv_machine_timer_t;
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static volatile riscv_machine_timer_t *mtime =
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(riscv_machine_timer_t *)RISCV_MTIME_BASE;
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static volatile riscv_machine_timer_t *mtimecmp =
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(riscv_machine_timer_t *)RISCV_MTIMECMP_BASE;
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/*
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* The RISCV machine-mode timer is a one shot timer that needs to be rearm upon
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* every interrupt. Timer clock is a 64-bits ART.
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* To arm timer, we need to read the RTC value and update the
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* timer compare register by the RTC value + time interval we want timer
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* to interrupt.
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*/
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static ALWAYS_INLINE void riscv_machine_rearm_timer(void)
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{
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uint64_t rtc;
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/*
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* Following machine-mode timer implementation in QEMU, the actual
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* RTC read is performed when reading low timer value register.
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* Reading high timer value just reads the most significant 32-bits
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* of a cache value, obtained from a previous read to the low
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* timer value register. Hence, always read timer->val_low first.
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* This also works for other implementations.
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*/
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rtc = mtime->val_low;
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rtc |= ((uint64_t)mtime->val_high << 32);
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/*
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* Rearm timer to generate an interrupt after
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* sys_clock_hw_cycles_per_tick
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*/
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rtc += sys_clock_hw_cycles_per_tick;
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mtimecmp->val_low = (uint32_t)(rtc & 0xffffffff);
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mtimecmp->val_high = (uint32_t)((rtc >> 32) & 0xffffffff);
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}
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static void riscv_machine_timer_irq_handler(void *unused)
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{
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ARG_UNUSED(unused);
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_sys_clock_tick_announce();
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/* Rearm timer */
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riscv_machine_rearm_timer();
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}
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#ifdef CONFIG_TICKLESS_IDLE
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#error "Tickless idle not yet implemented for riscv-machine timer"
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#endif
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int _sys_clock_driver_init(struct device *device)
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{
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ARG_UNUSED(device);
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IRQ_CONNECT(RISCV_MACHINE_TIMER_IRQ, 0,
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riscv_machine_timer_irq_handler, NULL, 0);
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irq_enable(RISCV_MACHINE_TIMER_IRQ);
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/* Initialize timer, just call riscv_machine_rearm_timer */
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riscv_machine_rearm_timer();
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return 0;
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}
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/**
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*
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* @brief Read the platform's timer hardware
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*
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* This routine returns the current time in terms of timer hardware clock
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* cycles.
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*
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* @return up counter of elapsed clock cycles
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*/
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uint32_t _timer_cycle_get_32(void)
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{
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/* We just want a cycle count so just post what's in the low 32
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* bits of the mtime real-time counter
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*/
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return mtime->val_low;
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}
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