39433f0669
Define all the register offset directly in the driver according to the RISCV PLIC specification as they are not configurable, see: https://github.com/riscv/riscv-plic-spec. Updated devicetrees that has PLIC accordingly. Signed-off-by: Yong Cong Sin <ycsin@meta.com>
264 lines
6.7 KiB
C
264 lines
6.7 KiB
C
/*
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* Copyright (c) 2017 Jean-Paul Etienne <fractalclone@gmail.com>
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* Contributors: 2018 Antmicro <www.antmicro.com>
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sifive_plic_1_0_0
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/**
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* @brief Platform Level Interrupt Controller (PLIC) driver
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* for RISC-V processors
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/arch/cpu.h>
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#include <zephyr/device.h>
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#include <soc.h>
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#include <zephyr/sw_isr_table.h>
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#include <zephyr/drivers/interrupt_controller/riscv_plic.h>
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#include <zephyr/irq.h>
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#define PLIC_BASE_ADDR(n) DT_INST_REG_ADDR(n)
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/*
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* These registers' offset are defined in the RISCV PLIC specs, see:
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* https://github.com/riscv/riscv-plic-spec
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*/
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#define PLIC_REG_PRIO_OFFSET 0x0
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#define PLIC_REG_IRQ_EN_OFFSET 0x2000
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#define PLIC_REG_REGS_OFFSET 0x200000
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/*
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* Trigger type is mentioned, but not defined in the RISCV PLIC specs.
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* However, it is defined and supported by at least the Andes & Telink datasheet, and supported
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* in Linux's SiFive PLIC driver
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*/
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#define PLIC_REG_TRIG_TYPE_OFFSET 0x1080
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#define PLIC_MAX_PRIO DT_INST_PROP(0, riscv_max_priority)
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#define PLIC_PRIO (PLIC_BASE_ADDR(0) + PLIC_REG_PRIO_OFFSET)
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#define PLIC_IRQ_EN (PLIC_BASE_ADDR(0) + PLIC_REG_IRQ_EN_OFFSET)
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#define PLIC_REG (PLIC_BASE_ADDR(0) + PLIC_REG_REGS_OFFSET)
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#define PLIC_IRQS (CONFIG_NUM_IRQS - CONFIG_2ND_LVL_ISR_TBL_OFFSET)
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#define PLIC_EN_SIZE ((PLIC_IRQS >> 5) + 1)
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#define PLIC_EDGE_TRIG_TYPE (PLIC_BASE_ADDR(0) + PLIC_REG_TRIG_TYPE_OFFSET)
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#define PLIC_EDGE_TRIG_SHIFT 5
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struct plic_regs_t {
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uint32_t threshold_prio;
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uint32_t claim_complete;
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};
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static int save_irq;
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/**
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* @brief return edge irq value or zero
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*
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* In the event edge irq is enable this will return the trigger
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* value of the irq. In the event edge irq is not supported this
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* routine will return 0
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*
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* @param irq IRQ number to add to the trigger
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*
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* @return irq value when enabled 0 otherwise
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*/
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static int riscv_plic_is_edge_irq(uint32_t irq)
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{
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volatile uint32_t *trig = (volatile uint32_t *)PLIC_EDGE_TRIG_TYPE;
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trig += (irq >> PLIC_EDGE_TRIG_SHIFT);
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return *trig & BIT(irq);
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}
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/**
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* @brief Enable a riscv PLIC-specific interrupt line
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*
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* This routine enables a RISCV PLIC-specific interrupt line.
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* riscv_plic_irq_enable is called by SOC_FAMILY_RISCV_PRIVILEGED
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* arch_irq_enable function to enable external interrupts for
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* IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
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*
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* @param irq IRQ number to enable
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*/
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void riscv_plic_irq_enable(uint32_t irq)
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{
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uint32_t key;
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volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
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key = irq_lock();
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en += (irq >> 5);
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*en |= (1 << (irq & 31));
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irq_unlock(key);
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}
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/**
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* @brief Disable a riscv PLIC-specific interrupt line
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*
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* This routine disables a RISCV PLIC-specific interrupt line.
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* riscv_plic_irq_disable is called by SOC_FAMILY_RISCV_PRIVILEGED
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* arch_irq_disable function to disable external interrupts, for
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* IRQS level == 2, whenever CONFIG_RISCV_HAS_PLIC variable is set.
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*
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* @param irq IRQ number to disable
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*/
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void riscv_plic_irq_disable(uint32_t irq)
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{
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uint32_t key;
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volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
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key = irq_lock();
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en += (irq >> 5);
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*en &= ~(1 << (irq & 31));
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irq_unlock(key);
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}
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/**
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* @brief Check if a riscv PLIC-specific interrupt line is enabled
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*
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* This routine checks if a RISCV PLIC-specific interrupt line is enabled.
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* @param irq IRQ number to check
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*
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* @return 1 or 0
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*/
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int riscv_plic_irq_is_enabled(uint32_t irq)
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{
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volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
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en += (irq >> 5);
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return !!(*en & (1 << (irq & 31)));
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}
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/**
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* @brief Set priority of a riscv PLIC-specific interrupt line
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*
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* This routine set the priority of a RISCV PLIC-specific interrupt line.
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* riscv_plic_irq_set_prio is called by riscv arch_irq_priority_set to set
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* the priority of an interrupt whenever CONFIG_RISCV_HAS_PLIC variable is set.
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*
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* @param irq IRQ number for which to set priority
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* @param priority Priority of IRQ to set to
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*/
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void riscv_plic_set_priority(uint32_t irq, uint32_t priority)
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{
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volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
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if (priority > PLIC_MAX_PRIO)
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priority = PLIC_MAX_PRIO;
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prio += irq;
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*prio = priority;
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}
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/**
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* @brief Get riscv PLIC-specific interrupt line causing an interrupt
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*
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* This routine returns the RISCV PLIC-specific interrupt line causing an
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* interrupt.
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*
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* @return PLIC-specific interrupt line causing an interrupt.
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*/
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int riscv_plic_get_irq(void)
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{
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return save_irq;
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}
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static void plic_irq_handler(const void *arg)
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{
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volatile struct plic_regs_t *regs =
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(volatile struct plic_regs_t *) PLIC_REG;
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uint32_t irq;
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struct _isr_table_entry *ite;
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int edge_irq;
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/* Get the IRQ number generating the interrupt */
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irq = regs->claim_complete;
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/*
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* Save IRQ in save_irq. To be used, if need be, by
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* subsequent handlers registered in the _sw_isr_table table,
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* as IRQ number held by the claim_complete register is
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* cleared upon read.
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*/
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save_irq = irq;
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/*
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* If the IRQ is out of range, call z_irq_spurious.
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* A call to z_irq_spurious will not return.
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*/
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if (irq == 0U || irq >= PLIC_IRQS)
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z_irq_spurious(NULL);
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edge_irq = riscv_plic_is_edge_irq(irq);
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/*
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* For edge triggered interrupts, write to the claim_complete register
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* to indicate to the PLIC controller that the IRQ has been handled
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* for edge triggered interrupts.
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*/
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if (edge_irq)
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regs->claim_complete = save_irq;
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irq += CONFIG_2ND_LVL_ISR_TBL_OFFSET;
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/* Call the corresponding IRQ handler in _sw_isr_table */
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ite = (struct _isr_table_entry *)&_sw_isr_table[irq];
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ite->isr(ite->arg);
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/*
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* Write to claim_complete register to indicate to
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* PLIC controller that the IRQ has been handled
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* for level triggered interrupts.
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*/
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if (!edge_irq)
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regs->claim_complete = save_irq;
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}
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/**
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* @brief Initialize the Platform Level Interrupt Controller
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*
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* @retval 0 on success.
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*/
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static int plic_init(const struct device *dev)
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{
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volatile uint32_t *en = (volatile uint32_t *)PLIC_IRQ_EN;
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volatile uint32_t *prio = (volatile uint32_t *)PLIC_PRIO;
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volatile struct plic_regs_t *regs =
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(volatile struct plic_regs_t *)PLIC_REG;
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int i;
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/* Ensure that all interrupts are disabled initially */
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for (i = 0; i < PLIC_EN_SIZE; i++) {
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*en = 0U;
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en++;
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}
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/* Set priority of each interrupt line to 0 initially */
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for (i = 0; i < PLIC_IRQS; i++) {
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*prio = 0U;
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prio++;
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}
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/* Set threshold priority to 0 */
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regs->threshold_prio = 0U;
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/* Setup IRQ handler for PLIC driver */
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IRQ_CONNECT(RISCV_MACHINE_EXT_IRQ,
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0,
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plic_irq_handler,
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NULL,
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0);
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/* Enable IRQ for PLIC driver */
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irq_enable(RISCV_MACHINE_EXT_IRQ);
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return 0;
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}
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DEVICE_DT_INST_DEFINE(0, plic_init, NULL, NULL, NULL,
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PRE_KERNEL_1, CONFIG_INTC_INIT_PRIORITY, NULL);
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