5b3d4598a7
This removes all occurrences of arm,num-mpu-regions relying on the value reported by the register instead. A user may still define this property if they need to have a compile time definition for it. Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
66 lines
1.1 KiB
Plaintext
66 lines
1.1 KiB
Plaintext
/*
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* Copyright (c) 2018 Nordic Semiconductor ASA
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv8-m.dtsi>
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#include "nrf_common.dtsi"
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-m33f";
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reg = <0>;
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#address-cells = <1>;
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#size-cells = <1>;
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mpu: mpu@e000ed90 {
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compatible = "arm,armv8m-mpu";
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reg = <0xe000ed90 0x40>;
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};
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};
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};
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chosen {
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zephyr,entropy = &psa_rng;
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zephyr,flash-controller = &flash_controller;
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};
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soc {
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sram0: memory@20000000 {
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compatible = "mmio-sram";
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};
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peripheral@40000000 {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges = <0x0 0x40000000 0x10000000>;
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/* Common nRF91 peripherals description. */
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#include "nrf91_peripherals.dtsi"
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};
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/* Additional Non-Secure peripherals */
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gpiote: gpiote@40031000 {
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compatible = "nordic,nrf-gpiote";
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reg = <0x40031000 0x1000>;
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interrupts = <49 5>;
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status = "disabled";
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};
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};
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psa_rng: psa-rng {
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compatible = "zephyr,psa-crypto-rng";
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status = "okay";
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};
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};
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&nvic {
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arm,num-irq-priority-bits = <3>;
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};
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