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zephyr/dts/arm/nxp/nxp_rt10xx.dtsi
Wilfried Chauveau 5b3d4598a7 dts: arm: Blanket remove all usages of arm,num-mpu-regions 
This removes all occurrences of arm,num-mpu-regions relying on the value
reported by the register instead.
A user may still define this property if they need to have a compile time
definition for it.

Signed-off-by: Wilfried Chauveau <wilfried.chauveau@arm.com>
2023-12-01 10:48:00 +00:00

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/*
* Copyright 2017,2023 NXP
*
* SPDX-License-Identifier: Apache-2.0
*/
#include <mem.h>
#include <arm/armv7-m.dtsi>
#include <zephyr/dt-bindings/adc/adc.h>
#include <zephyr/dt-bindings/clock/imx_ccm.h>
#include <zephyr/dt-bindings/gpio/gpio.h>
#include <zephyr/dt-bindings/i2c/i2c.h>
#include <zephyr/dt-bindings/pwm/pwm.h>
#include <zephyr/dt-bindings/memory-controller/nxp,flexram.h>
/ {
chosen {
zephyr,entropy = &trng;
die-temp0 = &tempmon;
};
cpus {
#address-cells = <1>;
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-m7";
d-cache-line-size = <32>;
reg = <0>;
cpu-power-states = <&idle &suspend>;
#address-cells = <1>;
#size-cells = <1>;
mpu: mpu@e000ed90 {
compatible = "arm,armv7m-mpu";
reg = <0xe000ed90 0x40>;
};
itm: itm@e0000000 {
compatible = "arm,armv7m-itm";
reg = <0xe0000000 0x1000>;
swo-ref-frequency = <132000000>;
};
};
power-states {
idle: idle {
compatible = "zephyr,power-state";
power-state-name = "runtime-idle";
exit-latency-us = <4000>;
min-residency-us = <5000>;
};
suspend: suspend {
compatible = "zephyr,power-state";
power-state-name = "suspend-to-idle";
exit-latency-us = <5000>;
min-residency-us = <10000>;
};
};
};
sysclk: system-clock {
compatible = "fixed-clock";
clock-frequency = <600000000>;
#clock-cells = <0>;
};
xtal: clock-xtal {
compatible = "fixed-clock";
clock-frequency = <24000000>;
#clock-cells = <0>;
};
rtc_xtal: clock-rtc-xtal {
compatible = "fixed-clock";
clock-frequency = <32768>;
#clock-cells = <0>;
};
/* USB PLL (selected to be FLEXSPI clock source) will be left unchanged */
usbclk: usbpll-clock {
compatible = "fixed-clock";
clock-frequency = <480000000>;
#clock-cells = <0>;
};
soc {
flexram: flexram@400b0000 {
compatible = "nxp,flexram";
reg = <0x400b0000 0x4000>;
interrupts = <38 0>;
#address-cells = <1>;
#size-cells = <1>;
status = "okay";
flexram,bank-size = <32>;
itcm: itcm@0 {
compatible = "zephyr,memory-region", "nxp,imx-itcm";
reg = <0x00000000 DT_SIZE_K(128)>;
zephyr,memory-region = "ITCM";
};
dtcm: dtcm@20000000 {
compatible = "zephyr,memory-region", "nxp,imx-dtcm";
reg = <0x20000000 DT_SIZE_K(128)>;
zephyr,memory-region = "DTCM";
};
ocram: ocram@20200000 {
compatible = "zephyr,memory-region", "mmio-sram";
reg = <0x20200000 DT_SIZE_K(256)>;
zephyr,memory-region = "OCRAM";
};
};
flexspi: spi@402a8000 {
compatible = "nxp,imx-flexspi";
reg = <0x402a8000 0x4000>;
interrupts = <108 0>;
#address-cells = <1>;
#size-cells = <0>;
ahb-bufferable;
ahb-cacheable;
status = "disabled";
};
flexspi2: spi@402a4000 {
compatible = "nxp,imx-flexspi";
reg = <0x402a4000 0x4000>;
interrupts = <107 0>;
#address-cells = <1>;
#size-cells = <0>;
ahb-bufferable;
ahb-cacheable;
status = "disabled";
};
semc: semc0@402f0000 {
compatible = "nxp,imx-semc";
reg = <0x402f0000 0x4000>;
interrupts = <109 0>;
#address-cells = <1>;
#size-cells = <1>;
};
/* GPT1 is used for the hardware timer, not as a standard counter */
gpt_hw_timer: gpt@401ec000 {
compatible = "nxp,gpt-hw-timer";
reg = <0x401ec000 0x4000>;
interrupts = <100 0>;
status = "disabled";
};
gpt2: gpt@401f0000 {
compatible = "nxp,imx-gpt";
reg = <0x401f0000 0x4000>;
interrupts = <101 0>;
gptfreq = <25000000>;
clocks = <&ccm IMX_CCM_GPT_CLK 0x68 24>;
};
qtmr1: qtmr@401dc000 {
compatible = "nxp,imx-qtmr";
reg = <0x401dc000 0x7a>;
interrupts = <133 0>;
clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
qtmr1_timer0: timer0 {
compatible = "nxp,imx-tmr";
channel = <0>;
status = "disabled";
};
qtmr1_timer1: timer1 {
compatible = "nxp,imx-tmr";
channel = <1>;
status = "disabled";
};
qtmr1_timer2: timer2 {
compatible = "nxp,imx-tmr";
channel = <2>;
status = "disabled";
};
qtmr1_timer3: timer3 {
compatible = "nxp,imx-tmr";
channel = <3>;
status = "disabled";
};
};
qtmr2: qtmr@401e0000 {
compatible = "nxp,imx-qtmr";
reg = <0x401e0000 0x7a>;
interrupts = <134 0>;
clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
qtmr2_timer0: timer0 {
compatible = "nxp,imx-tmr";
channel = <0>;
status = "disabled";
};
qtmr2_timer1: timer1 {
compatible = "nxp,imx-tmr";
channel = <1>;
status = "disabled";
};
qtmr2_timer2: timer2 {
compatible = "nxp,imx-tmr";
channel = <2>;
status = "disabled";
};
qtmr2_timer3: timer3 {
compatible = "nxp,imx-tmr";
channel = <3>;
status = "disabled";
};
};
qtmr3: qtmr@401e4000 {
compatible = "nxp,imx-qtmr";
reg = <0x401e4000 0x7a>;
interrupts = <135 0>;
clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
qtmr3_timer0: timer0 {
compatible = "nxp,imx-tmr";
channel = <0>;
status = "disabled";
};
qtmr3_timer1: timer1 {
compatible = "nxp,imx-tmr";
channel = <1>;
status = "disabled";
};
qtmr3_timer2: timer2 {
compatible = "nxp,imx-tmr";
channel = <2>;
status = "disabled";
};
qtmr3_timer3: timer3 {
compatible = "nxp,imx-tmr";
channel = <3>;
status = "disabled";
};
};
qtmr4: qtmr@401e8000 {
compatible = "nxp,imx-qtmr";
reg = <0x401e8000 0x7a>;
interrupts = <136 0>;
clocks = <&ccm IMX_CCM_QTMR_CLK 0 0>;
qtmr4_timer0: timer0 {
compatible = "nxp,imx-tmr";
channel = <0>;
status = "disabled";
};
qtmr4_timer1: timer1 {
compatible = "nxp,imx-tmr";
channel = <1>;
status = "disabled";
};
qtmr4_timer2: timer2 {
compatible = "nxp,imx-tmr";
channel = <2>;
status = "disabled";
};
qtmr4_timer3: timer3 {
compatible = "nxp,imx-tmr";
channel = <3>;
status = "disabled";
};
};
ccm: ccm@400fc000 {
compatible = "nxp,imx-ccm";
reg = <0x400fc000 0x4000>;
clocks = <&xtal>, <&rtc_xtal>;
clock-names = "xtal", "rtc-xtal";
arm-podf {
compatible = "fixed-factor-clock";
clock-div = <1>;
#clock-cells = <0>;
};
ahb-podf {
compatible = "fixed-factor-clock";
clock-div = <1>;
#clock-cells = <0>;
};
ipg-podf {
compatible = "fixed-factor-clock";
clock-div = <1>;
#clock-cells = <0>;
};
#clock-cells = <3>;
};
snvs: snvs@400d4000 {
compatible = "nxp,imx-snvs";
reg = <0x400d4000 0x4000>;
snvs_rtc: rtc {
compatible = "nxp,imx-snvs-rtc";
interrupts = <46 0>;
};
};
gpio1: gpio@401b8000 {
compatible = "nxp,imx-gpio";
reg = <0x401b8000 0x4000>;
interrupts = <80 0>, <81 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio2: gpio@401bc000 {
compatible = "nxp,imx-gpio";
reg = <0x401bc000 0x4000>;
interrupts = <82 0>, <83 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio3: gpio@401c0000 {
compatible = "nxp,imx-gpio";
reg = <0x401c0000 0x4000>;
interrupts = <84 0>, <85 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio4: gpio@401c4000 {
compatible = "nxp,imx-gpio";
reg = <0x401c4000 0x4000>;
interrupts = <86 0>, <87 0>;
gpio-controller;
#gpio-cells = <2>;
};
gpio5: gpio@400c0000 {
compatible = "nxp,imx-gpio";
reg = <0x400c0000 0x4000>;
interrupts = <88 0>, <89 0>;
gpio-controller;
#gpio-cells = <2>;
};
/*
* Note: interrupts for GPIO6-9 are not currently supported
* by the gpio driver.
*/
gpio6: gpio@42000000 {
compatible = "nxp,imx-gpio";
reg = <0x42000000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio7: gpio@42004000 {
compatible = "nxp,imx-gpio";
reg = <0x42004000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio8: gpio@42008000 {
compatible = "nxp,imx-gpio";
reg = <0x42008000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
};
gpio9: gpio@4200c000 {
compatible = "nxp,imx-gpio";
reg = <0x4200c000 0x4000>;
gpio-controller;
#gpio-cells = <2>;
};
lpi2c1: i2c@403f0000 {
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403f0000 0x4000>;
interrupts = <28 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 6>;
status = "disabled";
};
lpi2c2: i2c@403f4000 {
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403f4000 0x4000>;
interrupts = <29 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 8>;
status = "disabled";
};
lpi2c3: i2c@403f8000 {
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403f8000 0x4000>;
interrupts = <30 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x70 10>;
status = "disabled";
};
lpi2c4: i2c@403fc000 {
compatible = "nxp,imx-lpi2c";
clock-frequency = <I2C_BITRATE_STANDARD>;
#address-cells = <1>;
#size-cells = <0>;
reg = <0x403fc000 0x4000>;
interrupts = <31 0>;
clocks = <&ccm IMX_CCM_LPI2C_CLK 0x80 24>;
status = "disabled";
};
iomuxc: iomuxc@401f8000 {
compatible = "nxp,imx-iomuxc";
reg = <0x401f8000 0x4000>;
status = "okay";
pinctrl: pinctrl {
status = "okay";
compatible = "nxp,mcux-rt-pinctrl";
};
};
lcdif: display-controller@402b8000 {
compatible = "nxp,imx-elcdif";
reg = <0x402b8000 0x4000>;
interrupts = <42 0>;
status = "disabled";
nxp,pxp = <&pxp>;
};
lpspi1: spi@40394000 {
compatible = "nxp,imx-lpspi";
reg = <0x40394000 0x4000>;
interrupts = <32 3>;
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 0>;
#address-cells = <1>;
#size-cells = <0>;
};
lpspi2: spi@40398000 {
compatible = "nxp,imx-lpspi";
reg = <0x40398000 0x4000>;
interrupts = <33 3>;
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 2>;
#address-cells = <1>;
#size-cells = <0>;
};
lpspi3: spi@4039c000 {
compatible = "nxp,imx-lpspi";
reg = <0x4039c000 0x4000>;
interrupts = <34 3>;
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 4>;
#address-cells = <1>;
#size-cells = <0>;
};
lpspi4: spi@403a0000 {
compatible = "nxp,imx-lpspi";
reg = <0x403a0000 0x4000>;
interrupts = <35 3>;
status = "disabled";
clocks = <&ccm IMX_CCM_LPSPI_CLK 0x6c 6>;
#address-cells = <1>;
#size-cells = <0>;
};
lpuart1: uart@40184000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40184000 0x4000>;
interrupts = <20 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 24>;
dmas = <&edma0 1 2>, <&edma0 2 3>;
dma-names = "tx", "rx";
status = "disabled";
};
lpuart2: uart@40188000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40188000 0x4000>;
interrupts = <21 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 28>;
dmas = <&edma0 3 66>, <&edma0 4 67>;
dma-names = "tx", "rx";
status = "disabled";
};
lpuart3: uart@4018c000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4018c000 0x4000>;
interrupts = <22 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x68 12>;
dmas = <&edma0 5 4>, <&edma0 6 5>;
dma-names = "tx", "rx";
status = "disabled";
};
lpuart4: uart@40190000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40190000 0x4000>;
interrupts = <23 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x6c 24>;
dmas = <&edma0 7 68>, <&edma0 8 69>;
dma-names = "tx", "rx";
status = "disabled";
};
lpuart5: uart@40194000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40194000 0x4000>;
interrupts = <24 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 2>;
dmas = <&edma0 9 6>, <&edma0 10 7>;
dma-names = "tx", "rx";
status = "disabled";
};
lpuart6: uart@40198000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x40198000 0x4000>;
interrupts = <25 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x74 6>;
dmas = <&edma0 11 70>, <&edma0 12 71>;
dma-names = "tx", "rx";
status = "disabled";
};
lpuart7: uart@4019c000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x4019c000 0x4000>;
interrupts = <26 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x7c 26>;
dmas = <&edma0 13 8>, <&edma0 14 9>;
dma-names = "tx", "rx";
status = "disabled";
};
lpuart8: uart@401a0000 {
compatible = "nxp,kinetis-lpuart";
reg = <0x401a0000 0x4000>;
interrupts = <27 0>;
clocks = <&ccm IMX_CCM_LPUART_CLK 0x80 14>;
dmas = <&edma0 15 72>, <&edma0 16 73>;
dma-names = "tx", "rx";
status = "disabled";
};
adc1: adc@400c4000 {
compatible = "nxp,mcux-12b1msps-sar";
reg = <0x400C4000 0x1000>;
interrupts = <67 0>;
clk-divider = <1>;
sample-period-mode = <0>;
status = "disabled";
#io-channel-cells = <1>;
};
adc2: adc@400c8000 {
compatible = "nxp,mcux-12b1msps-sar";
reg = <0x400C8000 0x1000>;
interrupts = <68 0>;
clk-divider = <1>;
sample-period-mode = <0>;
status = "disabled";
#io-channel-cells = <1>;
};
flexpwm1: flexpwm@403dc000 {
compatible = "nxp,flexpwm";
reg = <0x403dc000 0x4000>;
interrupts = <106 0>;
flexpwm1_pwm0: flexpwm1_pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
interrupts = <102 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm1_pwm1: flexpwm1_pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
interrupts = <103 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm1_pwm2: flexpwm1_pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
interrupts = <104 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm1_pwm3: flexpwm1_pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
interrupts = <105 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
};
flexpwm2: flexpwm@403e0000 {
compatible = "nxp,flexpwm";
reg = <0x403e0000 0x4000>;
interrupts = <141 0>;
flexpwm2_pwm0: flexpwm2_pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
interrupts = <137 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm2_pwm1: flexpwm2_pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
interrupts = <138 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm2_pwm2: flexpwm2_pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
interrupts = <139 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm2_pwm3: flexpwm2_pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
interrupts = <140 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
};
flexpwm3: flexpwm@403e4000 {
compatible = "nxp,flexpwm";
reg = <0x403e4000 0x4000>;
interrupts = <146 0>;
flexpwm3_pwm0: flexpwm3_pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
interrupts = <142 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm3_pwm1: flexpwm3_pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
interrupts = <143 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm3_pwm2: flexpwm3_pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
interrupts = <144 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm3_pwm3: flexpwm3_pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
interrupts = <145 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
};
flexpwm4: flexpwm@403e8000 {
compatible = "nxp,flexpwm";
reg = <0x403e8000 0x4000>;
interrupts = <151 0>;
flexpwm4_pwm0: flexpwm4_pwm0 {
compatible = "nxp,imx-pwm";
index = <0>;
interrupts = <147 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm4_pwm1: flexpwm4_pwm1 {
compatible = "nxp,imx-pwm";
index = <1>;
interrupts = <148 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm4_pwm2: flexpwm4_pwm2 {
compatible = "nxp,imx-pwm";
index = <2>;
interrupts = <149 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
flexpwm4_pwm3: flexpwm4_pwm3 {
compatible = "nxp,imx-pwm";
index = <3>;
interrupts = <150 0>;
#pwm-cells = <3>;
clocks = <&ccm IMX_CCM_PWM_CLK 0 0>;
nxp,prescaler = <128>;
status = "disabled";
};
};
enet: ethernet@402d8000 {
compatible = "nxp,kinetis-ethernet";
reg = <0x402D8000 0x628>;
interrupts = <114 0>;
interrupt-names = "COMMON";
status = "disabled";
phy-addr = <0>;
ptp: ptp {
compatible = "nxp,kinetis-ptp";
status = "disabled";
interrupts = <115 0>;
interrupt-names = "IEEE1588_TMR";
};
};
src: reset-controller@400f8000 {
compatible = "nxp,imx-src";
reg = <0x400f8000 0x4000>;
status = "okay";
};
trng: random@400cc000 {
compatible = "nxp,kinetis-trng";
reg = <0x400cc000 0x4000>;
status = "okay";
interrupts = <53 0>;
};
usb1: usbd@402e0000 {
compatible = "nxp,ehci";
reg = <0x402E0000 0x200>;
interrupts = <113 1>;
interrupt-names = "usb_otg";
clocks = <&usbclk>;
num-bidir-endpoints = <8>;
status = "disabled";
};
usb2: usbd@402e0200 {
compatible = "nxp,ehci";
reg = <0x402E0200 0x200>;
interrupts = <112 1>;
interrupt-names = "usb_otg";
clocks = <&usbclk>;
num-bidir-endpoints = <8>;
status = "disabled";
};
usdhc1: usdhc@402c0000 {
compatible = "nxp,imx-usdhc";
reg = <0x402c0000 0x4000>;
status = "disabled";
interrupts = <110 0>;
clocks = <&ccm IMX_CCM_USDHC1_CLK 0 0>;
max-current-330 = <1020>;
max-current-180 = <1020>;
max-bus-freq = <208000000>;
min-bus-freq = <400000>;
};
usdhc2: usdhc@402c4000 {
compatible = "nxp,imx-usdhc";
reg = <0x402c4000 0x4000>;
status = "disabled";
interrupts = <111 0>;
clocks = <&ccm IMX_CCM_USDHC2_CLK 0 0>;
max-current-330 = <120>;
max-current-180 = <45>;
max-bus-freq = <198000000>;
min-bus-freq = <400000>;
};
csi: csi@402bc000 {
compatible = "nxp,imx-csi";
reg = <0x402BC000 0x4000>;
interrupts = <43 1>;
status = "disabled";
};
edma0: dma-controller@400e8000 {
#dma-cells = <2>;
compatible = "nxp,mcux-edma";
dma-channels = <32>;
dma-requests = <128>;
nxp,mem2mem;
nxp,a_on;
reg = <0x400E8000 0x4000>,
<0x400EC000 0x4000>;
interrupts = <0 0>, <1 0>, <2 0>, <3 0>,
<4 0>, <5 0>, <6 0>, <7 0>,
<8 0>, <9 0>, <10 0>, <11 0>,
<12 0>, <13 0>, <14 0>, <15 0>,
<16 0>;
irq-shared-offset = <16>;
clocks = <&ccm IMX_CCM_EDMA_CLK 0x7C 0x000000C0>;
status = "disabled";
};
flexcan1: can@401d0000 {
compatible = "nxp,flexcan";
reg = <0x401d0000 0x1000>;
interrupts = <36 0>;
interrupt-names = "common";
clocks = <&ccm IMX_CCM_CAN_CLK 0x68 14>;
clk-source = <2>;
sample-point = <875>;
status = "disabled";
};
flexcan2: can@401d4000 {
compatible = "nxp,flexcan";
reg = <0x401d4000 0x1000>;
interrupts = <37 0>;
interrupt-names = "common";
clocks = <&ccm IMX_CCM_CAN_CLK 0x68 18>;
clk-source = <2>;
sample-point = <875>;
status = "disabled";
};
flexcan3: can@401d8000 {
compatible = "nxp,flexcan-fd", "nxp,flexcan";
reg = <0x401d8000 0x1000>;
interrupts = <154 0>;
interrupt-names = "common";
clocks = <&ccm IMX_CCM_CAN_CLK 0x84 6>;
clk-source = <2>;
sample-point = <875>;
sample-point-data = <875>;
status = "disabled";
};
wdog0: wdog@400b8000 {
compatible = "nxp,imx-wdog";
reg = <0x400b8000 0xA>;
status = "disabled";
interrupts = <92 0>;
};
wdog1: wdog@400d0000 {
compatible = "nxp,imx-wdog";
reg = <0x400d0000 0xA>;
status = "disabled";
interrupts = <45 0>;
};
anatop: anatop@400d8000 {
compatible = "nxp,imx-anatop";
reg = <0x400d8000 0x4000>;
#clock-cells = <4>;
#pll-clock-cells = <3>;
};
iomuxcgpr: iomuxcgpr@400ac000 {
compatible = "nxp,imx-gpr";
reg = <0x400AC000 0x4000>;
#pinmux-cells = <2>;
};
pxp: pxp@402b4000 {
compatible = "nxp,pxp";
reg = <0x402b4000 0x4000>;
interrupts = <44 0>;
status = "disabled";
#dma-cells = <0>;
};
sai1: sai@40384000 {
compatible = "nxp,mcux-i2s";
#address-cells = <1>;
#size-cells = <0>;
#pinmux-cells = <2>;
reg = <0x40384000 0x4000>;
clocks = <&ccm IMX_CCM_SAI1_CLK 0x7C 18>;
/* Source clock from Audio PLL */
clock-mux = <2>;
/* Audio PLL Output Frequency is determined by:
* (Fref * (DIV_SELECT + NUM/DENOM)) / POST_DIV
* = (24MHz * (32 + 77 / 100)) / 1 = 786.48 MHz
*/
pll-clocks = <&anatop 0x70 0xC000 0>,
<&anatop 0x70 0x7F 32>,
<&anatop 0x70 0x180000 1>,
<&anatop 0x80 0x3FFFFFFF 77>,
<&anatop 0x90 0x3FFFFFFF 100>;
pll-clock-names = "src", "lp", "pd", "num", "den";
/* The maximum input frequency into the SAI mclk input is 300MHz
* Based on this requirement, pre-div must be at least 3
* The pre-div and post-div are one less than the actual divide-by amount.
* A pre-div value of 0x1 results in a pre-divider of
* (1+1) = 2
*/
pre-div = <0x3>;
podf = <0x0F>;
pinmuxes = <&iomuxcgpr 0x4 0x80000>;
interrupts = <56 0>;
dmas = <&edma0 0 19>, <&edma0 0 20>;
dma-names = "rx", "tx";
/* This translates to SAIChannelMask (fsl_sai.c) and
* cannot be 0
*/
nxp,tx-channel = <1>;
nxp,tx-dma-channel = <0>;
nxp,rx-dma-channel = <1>;
status = "disabled";
};
sai2: sai@40388000 {
compatible = "nxp,mcux-i2s";
#address-cells = <1>;
#size-cells = <0>;
#pinmux-cells = <2>;
reg = <0x40388000 0x4000>;
clocks = <&ccm IMX_CCM_SAI2_CLK 0x7C 20>;
/* Source clock from Audio PLL */
clock-mux = <2>;
pre-div = <0>;
podf = <63>;
pll-clocks = <&anatop 0x70 0xC000 0x0>,
<&anatop 0x70 0x7F 32>,
<&anatop 0x70 0x180000 1>,
<&anatop 0x80 0x3FFFFFFF 77>,
<&anatop 0x90 0x3FFFFFFF 100>;
pll-clock-names = "src", "lp", "pd", "num", "den";
pinmuxes = <&iomuxcgpr 0x4 0x100000>;
interrupts = <57 0>;
dmas = <&edma0 0 21>, <&edma0 0 22>;
dma-names = "rx", "tx";
nxp,tx-channel = <0>;
nxp,tx-dma-channel = <3>;
nxp,rx-dma-channel = <4>;
status = "disabled";
};
sai3: sai@4038c000 {
compatible = "nxp,mcux-i2s";
#address-cells = <1>;
#size-cells = <0>;
#pinmux-cells = <2>;
reg = <0x4038C000 0x4000>;
clocks = <&ccm IMX_CCM_SAI3_CLK 0x7C 22>;
/* Source clock from Audio PLL */
clock-mux = <2>;
pre-div = <0>;
podf = <63>;
pll-clocks = <&anatop 0x70 0xC000 0>,
<&anatop 0x70 0x7F 32>,
<&anatop 0x70 0x180000 1>,
<&anatop 0x80 0x3FFFFFFF 77>,
<&anatop 0x90 0x3FFFFFFF 100>;
pll-clock-names = "src", "lp", "pd", "num", "den";
pinmuxes = <&iomuxcgpr 0x4 0x200000>;
interrupts = <58 0>, <59 0>;
dmas = <&edma0 0 83>, <&edma0 0 84>;
dma-names = "rx", "tx";
nxp,tx-channel = <0>;
nxp,tx-dma-channel = <5>;
nxp,rx-dma-channel = <6>;
status = "disabled";
};
qdec1: qdec@403c8000 {
compatible = "nxp,mcux-qdec";
reg = <0x403c8000 0x4000>;
interrupts = <129 0>;
status = "disabled";
};
qdec2: qdec@403cc000 {
compatible = "nxp,mcux-qdec";
reg = <0x403cc000 0x4000>;
interrupts = <130 0>;
status = "disabled";
};
qdec3: qdec@403d0000 {
compatible = "nxp,mcux-qdec";
reg = <0x403d0000 0x4000>;
interrupts = <131 0>;
status = "disabled";
};
qdec4: qdec@403d4000 {
compatible = "nxp,mcux-qdec";
reg = <0x403d4000 0x4000>;
interrupts = <132 0>;
status = "disabled";
};
xbar1: xbar1@403bc000 {
compatible = "nxp,mcux-xbar";
reg = <0x403bc000 0x4000>;
interrupts = <116 0>, <117 0>;
status = "disabled";
};
xbar2: xbar2@403c0000 {
compatible = "nxp,mcux-xbar";
reg = <0x403c0000 0x4000>;
status = "disabled";
};
xbar3: xbar3@403c4000 {
compatible = "nxp,mcux-xbar";
reg = <0x403c4000 0x4000>;
status = "disabled";
};
dcp: dcp@402fc000 {
compatible = "nxp,mcux-dcp";
reg = <0x402fc000 0x4000>;
interrupts = <50 0>, <51 0>;
status = "okay";
};
tempmon: tempmon@400d8000 {
compatible = "nxp,tempmon";
reg = <0x400d8000 0x2a0>;
status = "disabled";
};
};
};
&nvic {
arm,num-irq-priority-bits = <4>;
};
&systick {
/*
* RT10xx relies by default on the GPT Timer for system clock
* implementation, so the SysTick node should not be enabled.
*/
status = "disabled";
};
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