159fa4888b
Sometimes, channel C may write wrong register to the target device. This issue occurs when FIFO2 is enabled on channel C. The problem arises because FIFO2 is shared between channel B and channel C. FIFO2 will be disabled when data access is completed, at which point FIFO2 is set to the default configuration for channel B. The byte counter of FIFO2 may be affected by channel B. There is a chance that channel C may encounter wrong register being written due to the FIFO2 byte counter wrong write after channel B's write operation. The current workaround is that channel C cannot use FIFO mode. Signed-off-by: Tim Lin <tim2.lin@ite.corp-partner.google.com>
71 lines
1.8 KiB
Plaintext
71 lines
1.8 KiB
Plaintext
# Copyright (c) 2020 ITE Corporation. All Rights Reserved.
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# SPDX-License-Identifier: Apache-2.0
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config I2C_ITE_IT8XXX2
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bool "ITE IT8XXX2 I2C driver"
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default y
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depends on DT_HAS_ITE_IT8XXX2_I2C_ENABLED
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help
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Enable I2C support on it8xxx2_evb.
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Supported Speeds: 100kHz, 400kHz and 1MHz.
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This driver supports repeated start.
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if I2C_ITE_IT8XXX2
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config I2C_IT8XXX2_FIFO_MODE
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bool "IT8XXX2 I2C FIFO mode"
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default y
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help
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This is an option to enable FIFO mode which can reduce
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the time between each byte to improve the I2C bus clock
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stretching during I2C transaction.
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The I2C controller supports two 32-bytes FIFOs,
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FIFO1 supports channel A. FIFO2 supports channel B.
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I2C FIFO mode of it8xxx2 can support I2C APIs including:
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i2c_write(), i2c_read(), i2c_burst_read.
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endif # I2C_ITE_IT8XXX2
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config I2C_ITE_ENHANCE
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bool "ITE IT8XXX2 I2C enhance driver"
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default y
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depends on DT_HAS_ITE_ENHANCE_I2C_ENABLED
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help
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This option can enable the enhance I2C
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of IT8XXX2 and support three channels.
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if I2C_ITE_ENHANCE
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config I2C_IT8XXX2_CQ_MODE
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bool "IT8XXX2 I2C command queue mode"
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default y
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select SOC_IT8XXX2_CPU_IDLE_GATING
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help
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This is an option to enable command queue mode which can
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reduce the time between each byte to improve the I2C bus
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clock stretching during I2C transaction.
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I2C command queue mode of it8xxx2 can support I2C APIs
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including: i2c_write(), i2c_read(), i2c_burst_read.
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config I2C_CQ_MODE_MAX_PAYLOAD_SIZE
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int "It is allowed to configure the size up to 2K bytes."
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range 32 2048
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default 64
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help
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This is the command queue mode payload size which size
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up to 2k bytes.
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endif # I2C_ITE_ENHANCE
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if I2C_TARGET
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config I2C_TARGET_IT8XXX2_MAX_BUF_SIZE
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int "It is allowed to configure the size up to 2044 bytes."
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range 4 2044
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default 256
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config I2C_TARGET_BUFFER_MODE
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default y
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endif # I2C_TARGET
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