11d27f12ad
This commit drops the `IRAM_ATTR` macro from the function declarations because: 1. `IRAM_ATTR` macro makes use of the `__COUNTER__` preprocessor macro, which increments for every macro invocation and causes the section specified in the forward declaration to not match that of the function definition. 2. Section attributes need not be specified for forward declarations. Signed-off-by: Stephanos Ioannidis <root@stephanos.io>
483 lines
12 KiB
C
483 lines
12 KiB
C
/*
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* Copyright (c) 2017 Intel Corporation
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* Copyright (c) 2021 Espressif Systems (Shanghai) Co., Ltd.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT espressif_esp32_gpio
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/* Include esp-idf headers first to avoid redefining BIT() macro */
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#include <soc/gpio_reg.h>
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#include <soc/io_mux_reg.h>
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#include <soc/soc.h>
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#include <hal/gpio_ll.h>
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#include <esp_attr.h>
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#include <hal/rtc_io_hal.h>
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#include <soc.h>
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/drivers/gpio.h>
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#include <zephyr/dt-bindings/gpio/espressif-esp32-gpio.h>
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#ifdef CONFIG_SOC_ESP32C3
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#include <zephyr/drivers/interrupt_controller/intc_esp32c3.h>
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#else
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#include <zephyr/drivers/interrupt_controller/intc_esp32.h>
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#endif
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#include <zephyr/kernel.h>
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#include <zephyr/sys/util.h>
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#include "gpio_utils.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
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#ifdef CONFIG_SOC_ESP32C3
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/* gpio structs in esp32c3 series are different from xtensa ones */
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#define out out.data
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#define in in.data
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#define out_w1ts out_w1ts.val
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#define out_w1tc out_w1tc.val
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/* arch_curr_cpu() is not available for riscv based chips */
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#define CPU_ID() 0
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#define ISR_HANDLER isr_handler_t
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#else
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#define CPU_ID() arch_curr_cpu()->id
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#define ISR_HANDLER intr_handler_t
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#endif
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#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
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#define SOC_GPIO_SUPPORT_RTC_INDEPENDENT 0
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#endif
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struct gpio_esp32_config {
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/* gpio_driver_config needs to be first */
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struct gpio_driver_config drv_cfg;
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gpio_dev_t *const gpio_base;
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gpio_dev_t *const gpio_dev;
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const int gpio_port;
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};
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struct gpio_esp32_data {
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/* gpio_driver_data needs to be first */
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struct gpio_driver_data common;
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sys_slist_t cb;
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};
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static inline bool rtc_gpio_is_valid_gpio(uint32_t gpio_num)
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{
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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return (gpio_num < SOC_GPIO_PIN_COUNT && rtc_io_num_map[gpio_num] >= 0);
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#else
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return false;
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#endif
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}
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static inline bool gpio_pin_is_valid(uint32_t pin)
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{
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return ((BIT(pin) & SOC_GPIO_VALID_GPIO_MASK) != 0);
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}
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static inline bool gpio_pin_is_output_capable(uint32_t pin)
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{
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return ((BIT(pin) & SOC_GPIO_VALID_OUTPUT_GPIO_MASK) != 0);
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}
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static int gpio_esp32_config(const struct device *dev,
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gpio_pin_t pin,
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gpio_flags_t flags)
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{
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const struct gpio_esp32_config *const cfg = dev->config;
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struct gpio_esp32_data *data = dev->data;
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uint32_t io_pin = (uint32_t) pin + ((cfg->gpio_port == 1 && pin < 32) ? 32 : 0);
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uint32_t key;
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int ret = 0;
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if (!gpio_pin_is_valid(io_pin)) {
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LOG_ERR("Selected IO pin is not valid.");
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return -EINVAL;
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}
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key = irq_lock();
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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if (rtc_gpio_is_valid_gpio(io_pin)) {
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rtcio_hal_function_select(rtc_io_num_map[io_pin], RTCIO_FUNC_DIGITAL);
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}
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#endif
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if (io_pin >= GPIO_NUM_MAX) {
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LOG_ERR("Invalid pin.");
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ret = -EINVAL;
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goto end;
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}
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/* Set pin function as GPIO */
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gpio_ll_iomux_func_sel(GPIO_PIN_MUX_REG[io_pin], PIN_FUNC_GPIO);
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if (flags & GPIO_PULL_UP) {
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if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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gpio_ll_pulldown_dis(&GPIO, io_pin);
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gpio_ll_pullup_en(&GPIO, io_pin);
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} else {
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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int rtcio_num = rtc_io_num_map[io_pin];
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rtcio_hal_pulldown_disable(rtc_io_num_map[io_pin]);
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if (rtc_io_desc[rtcio_num].pullup) {
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rtcio_hal_pullup_enable(rtc_io_num_map[io_pin]);
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} else {
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ret = -ENOTSUP;
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goto end;
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}
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#endif
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}
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} else if (flags & GPIO_PULL_DOWN) {
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if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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gpio_ll_pullup_dis(&GPIO, io_pin);
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gpio_ll_pulldown_en(&GPIO, io_pin);
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} else {
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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int rtcio_num = rtc_io_num_map[io_pin];
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rtcio_hal_pulldown_enable(rtc_io_num_map[io_pin]);
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if (rtc_io_desc[rtcio_num].pullup) {
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rtcio_hal_pullup_disable(rtc_io_num_map[io_pin]);
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} else {
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ret = -ENOTSUP;
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goto end;
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}
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#endif
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}
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}
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if (flags & GPIO_OUTPUT) {
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if (!gpio_pin_is_output_capable(pin)) {
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LOG_ERR("GPIO can only be used as input");
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ret = -EINVAL;
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goto end;
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}
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if (flags & GPIO_SINGLE_ENDED) {
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if (flags & GPIO_LINE_OPEN_DRAIN) {
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gpio_ll_od_enable(cfg->gpio_base, io_pin);
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} else {
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LOG_ERR("GPIO configuration not supported");
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ret = -ENOTSUP;
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goto end;
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}
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} else {
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gpio_ll_od_disable(cfg->gpio_base, io_pin);
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}
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/*
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* By default, drive strength is set to its maximum value when the pin is set
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* to either low or high states. Alternative drive strength is weak-only,
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* while any other intermediary combination is considered invalid.
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*/
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switch (flags & ESP32_GPIO_DS_MASK) {
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case ESP32_GPIO_DS_DFLT:
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if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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gpio_ll_set_drive_capability(cfg->gpio_base,
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io_pin,
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GPIO_DRIVE_CAP_3);
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} else {
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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rtcio_hal_set_drive_capability(rtc_io_num_map[io_pin],
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GPIO_DRIVE_CAP_3);
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#endif
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}
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break;
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case ESP32_GPIO_DS_ALT:
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if (!rtc_gpio_is_valid_gpio(io_pin) || SOC_GPIO_SUPPORT_RTC_INDEPENDENT) {
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gpio_ll_set_drive_capability(cfg->gpio_base,
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io_pin,
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GPIO_DRIVE_CAP_0);
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} else {
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#if SOC_RTCIO_INPUT_OUTPUT_SUPPORTED
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rtcio_hal_set_drive_capability(rtc_io_num_map[io_pin],
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GPIO_DRIVE_CAP_0);
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#endif
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}
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break;
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default:
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ret = -EINVAL;
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goto end;
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}
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/* Set output pin initial value */
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if (flags & GPIO_OUTPUT_INIT_HIGH) {
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gpio_ll_set_level(cfg->gpio_base, io_pin, 1);
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} else if (flags & GPIO_OUTPUT_INIT_LOW) {
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gpio_ll_set_level(cfg->gpio_base, io_pin, 0);
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}
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gpio_ll_output_enable(&GPIO, io_pin);
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esp_rom_gpio_matrix_out(io_pin, SIG_GPIO_OUT_IDX, false, false);
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}
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if (flags & GPIO_INPUT) {
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gpio_ll_input_enable(&GPIO, io_pin);
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}
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end:
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irq_unlock(key);
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return ret;
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}
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static int gpio_esp32_port_get_raw(const struct device *port, uint32_t *value)
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{
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const struct gpio_esp32_config *const cfg = port->config;
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if (cfg->gpio_port == 0) {
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*value = cfg->gpio_dev->in;
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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} else {
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*value = cfg->gpio_dev->in1.data;
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#endif
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}
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return 0;
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}
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static int gpio_esp32_port_set_masked_raw(const struct device *port,
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uint32_t mask, uint32_t value)
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{
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const struct gpio_esp32_config *const cfg = port->config;
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uint32_t key = irq_lock();
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if (cfg->gpio_port == 0) {
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cfg->gpio_dev->out = (cfg->gpio_dev->out & ~mask) | (mask & value);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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} else {
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cfg->gpio_dev->out1.data = (cfg->gpio_dev->out1.data & ~mask) | (mask & value);
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#endif
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}
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irq_unlock(key);
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return 0;
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}
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static int gpio_esp32_port_set_bits_raw(const struct device *port,
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uint32_t pins)
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{
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const struct gpio_esp32_config *const cfg = port->config;
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if (cfg->gpio_port == 0) {
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cfg->gpio_dev->out_w1ts = pins;
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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} else {
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cfg->gpio_dev->out1_w1ts.data = pins;
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#endif
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}
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return 0;
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}
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static int gpio_esp32_port_clear_bits_raw(const struct device *port,
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uint32_t pins)
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{
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const struct gpio_esp32_config *const cfg = port->config;
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if (cfg->gpio_port == 0) {
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cfg->gpio_dev->out_w1tc = pins;
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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} else {
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cfg->gpio_dev->out1_w1tc.data = pins;
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#endif
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}
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return 0;
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}
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static int gpio_esp32_port_toggle_bits(const struct device *port,
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uint32_t pins)
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{
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const struct gpio_esp32_config *const cfg = port->config;
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uint32_t key = irq_lock();
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if (cfg->gpio_port == 0) {
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cfg->gpio_dev->out ^= pins;
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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} else {
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cfg->gpio_dev->out1.data ^= pins;
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#endif
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}
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irq_unlock(key);
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return 0;
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}
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static int convert_int_type(enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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if (mode == GPIO_INT_MODE_DISABLED) {
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return GPIO_INTR_DISABLE;
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}
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if (mode == GPIO_INT_MODE_LEVEL) {
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switch (trig) {
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case GPIO_INT_TRIG_LOW:
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return GPIO_INTR_LOW_LEVEL;
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case GPIO_INT_TRIG_HIGH:
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return GPIO_INTR_HIGH_LEVEL;
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default:
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return -EINVAL;
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}
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} else { /* edge interrupts */
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switch (trig) {
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case GPIO_INT_TRIG_HIGH:
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return GPIO_INTR_POSEDGE;
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case GPIO_INT_TRIG_LOW:
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return GPIO_INTR_NEGEDGE;
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case GPIO_INT_TRIG_BOTH:
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return GPIO_INTR_ANYEDGE;
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default:
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return -EINVAL;
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}
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}
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/* Any other type of interrupt triggering is invalid. */
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return -EINVAL;
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}
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static int gpio_esp32_pin_interrupt_configure(const struct device *port,
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gpio_pin_t pin,
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enum gpio_int_mode mode,
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enum gpio_int_trig trig)
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{
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const struct gpio_esp32_config *const cfg = port->config;
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uint32_t io_pin = (uint32_t) pin + ((cfg->gpio_port == 1 && pin < 32) ? 32 : 0);
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int intr_trig_mode = convert_int_type(mode, trig);
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uint32_t key;
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if (intr_trig_mode < 0) {
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return intr_trig_mode;
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}
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key = irq_lock();
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gpio_ll_set_intr_type(cfg->gpio_base, io_pin, intr_trig_mode);
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gpio_ll_intr_enable_on_core(cfg->gpio_base, CPU_ID(), io_pin);
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irq_unlock(key);
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return 0;
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}
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static int gpio_esp32_manage_callback(const struct device *dev,
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struct gpio_callback *callback,
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bool set)
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{
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struct gpio_esp32_data *data = dev->data;
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return gpio_manage_callback(&data->cb, callback, set);
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}
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static uint32_t gpio_esp32_get_pending_int(const struct device *dev)
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{
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const struct gpio_esp32_config *const cfg = dev->config;
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uint32_t irq_status;
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uint32_t const core_id = CPU_ID();
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if (cfg->gpio_port == 0) {
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gpio_ll_get_intr_status(cfg->gpio_base, core_id, &irq_status);
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} else {
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gpio_ll_get_intr_status_high(cfg->gpio_base, core_id, &irq_status);
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}
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return irq_status;
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}
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static void IRAM_ATTR gpio_esp32_fire_callbacks(const struct device *dev)
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{
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const struct gpio_esp32_config *const cfg = dev->config;
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struct gpio_esp32_data *data = dev->data;
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uint32_t irq_status;
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uint32_t const core_id = CPU_ID();
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if (cfg->gpio_port == 0) {
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gpio_ll_get_intr_status(cfg->gpio_base, core_id, &irq_status);
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gpio_ll_clear_intr_status(cfg->gpio_base, irq_status);
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} else {
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gpio_ll_get_intr_status_high(cfg->gpio_base, core_id, &irq_status);
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gpio_ll_clear_intr_status_high(cfg->gpio_base, irq_status);
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}
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if (irq_status != 0) {
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gpio_fire_callbacks(&data->cb, dev, irq_status);
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}
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}
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static void gpio_esp32_isr(void *param);
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static int gpio_esp32_init(const struct device *dev)
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{
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struct gpio_esp32_data *data = dev->data;
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static bool isr_connected;
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if (!isr_connected) {
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esp_intr_alloc(DT_IRQN(DT_NODELABEL(gpio0)),
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0,
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(ISR_HANDLER)gpio_esp32_isr,
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(void *)dev,
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NULL);
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isr_connected = true;
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}
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return 0;
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}
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static const struct gpio_driver_api gpio_esp32_driver_api = {
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.pin_configure = gpio_esp32_config,
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.port_get_raw = gpio_esp32_port_get_raw,
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.port_set_masked_raw = gpio_esp32_port_set_masked_raw,
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.port_set_bits_raw = gpio_esp32_port_set_bits_raw,
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.port_clear_bits_raw = gpio_esp32_port_clear_bits_raw,
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.port_toggle_bits = gpio_esp32_port_toggle_bits,
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.pin_interrupt_configure = gpio_esp32_pin_interrupt_configure,
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.manage_callback = gpio_esp32_manage_callback,
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.get_pending_int = gpio_esp32_get_pending_int
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};
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#define ESP_SOC_GPIO_INIT(_id) \
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static struct gpio_esp32_data gpio_data_##_id; \
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static struct gpio_esp32_config gpio_config_##_id = { \
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.drv_cfg = { \
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.port_pin_mask = GPIO_PORT_PIN_MASK_FROM_DT_INST(_id), \
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}, \
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.gpio_base = (gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio0)), \
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.gpio_dev = (gpio_dev_t *)DT_REG_ADDR(DT_NODELABEL(gpio##_id)), \
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.gpio_port = _id \
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}; \
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DEVICE_DT_DEFINE(DT_NODELABEL(gpio##_id), \
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&gpio_esp32_init, \
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NULL, \
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&gpio_data_##_id, \
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&gpio_config_##_id, \
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PRE_KERNEL_1, \
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CONFIG_GPIO_INIT_PRIORITY, \
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&gpio_esp32_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(ESP_SOC_GPIO_INIT);
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static void IRAM_ATTR gpio_esp32_isr(void *param)
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{
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ARG_UNUSED(param);
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio0), okay)
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gpio_esp32_fire_callbacks(DEVICE_DT_INST_GET(0));
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gpio1), okay)
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gpio_esp32_fire_callbacks(DEVICE_DT_INST_GET(1));
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#endif
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}
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