88ca215eed
Updates the API and types to match updated I2C terminology. Replaces master with controller and slave with target. Updates all drivers to match the changed macros, types, and API signatures. Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
383 lines
11 KiB
C
383 lines
11 KiB
C
/*
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* Copyright (c) 2021 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT renesas_rcar_i2c
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#include <errno.h>
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <soc.h>
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#include <zephyr/drivers/i2c.h>
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#include <zephyr/drivers/clock_control.h>
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#include <zephyr/drivers/clock_control/renesas_cpg_mssr.h>
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(i2c_rcar);
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#include "i2c-priv.h"
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typedef void (*init_func_t)(const struct device *dev);
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struct i2c_rcar_cfg {
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uint32_t reg_addr;
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init_func_t init_func;
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const struct device *clock_dev;
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struct rcar_cpg_clk mod_clk;
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uint32_t bitrate;
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};
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struct i2c_rcar_data {
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uint8_t status_mask;
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struct k_sem int_sem;
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};
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/* Registers */
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#define RCAR_I2C_ICSCR 0x00 /* Slave Control Register */
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#define RCAR_I2C_ICMCR 0x04 /* Master Control Register */
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#define RCAR_I2C_ICSIER 0x10 /* Slave IRQ Enable */
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#define RCAR_I2C_ICMIER 0x14 /* Master IRQ Enable */
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#define RCAR_I2C_ICSSR 0x08 /* Slave Status */
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#define RCAR_I2C_ICMSR 0x0c /* Master Status */
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#define RCAR_I2C_ICCCR 0x18 /* Clock Control Register */
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#define RCAR_I2C_ICSAR 0x1c /* Slave Address Register */
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#define RCAR_I2C_ICMAR 0x20 /* Master Address Register */
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#define RCAR_I2C_ICRXD_ICTXD 0x24 /* Receive Transmit Data Register */
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#define RCAR_I2C_ICFBSCR 0x38 /* First Bit Setup Cycle (Gen3).*/
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#define RCAR_I2C_ICFBSCR_TCYC17 0x0f /* 17*Tcyc */
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#define RCAR_I2C_ICMCR_MDBS BIT(7) /* Master Data Buffer Select */
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#define RCAR_I2C_ICMCR_FSCL BIT(6) /* Forced SCL */
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#define RCAR_I2C_ICMCR_FSDA BIT(5) /* Forced SDA */
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#define RCAR_I2C_ICMCR_OBPC BIT(4) /* Override Bus Pin Control */
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#define RCAR_I2C_ICMCR_MIE BIT(3) /* Master Interface Enable */
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#define RCAR_I2C_ICMCR_TSBE BIT(2) /* Start Byte Transmission Enable */
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#define RCAR_I2C_ICMCR_FSB BIT(1) /* Forced Stop onto the Bus */
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#define RCAR_I2C_ICMCR_ESG BIT(0) /* Enable Start Generation */
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#define RCAR_I2C_ICMCR_MASTER (RCAR_I2C_ICMCR_MDBS | RCAR_I2C_ICMCR_MIE)
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/* Bits to manage ICMIER and ICMSR registers */
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#define RCAR_I2C_MNR BIT(6) /* Master Nack Received */
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#define RCAR_I2C_MAL BIT(5) /* Master Arbitration lost */
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#define RCAR_I2C_MST BIT(4) /* Master Stop Transmitted */
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#define RCAR_I2C_MDE BIT(3) /* Master Data Empty */
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#define RCAR_I2C_MDT BIT(2) /* Master Data Transmitted */
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#define RCAR_I2C_MDR BIT(1) /* Master Data Received */
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#define RCAR_I2C_MAT BIT(0) /* Master Address Transmitted */
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/* Recommended bitrate settings from official documentation */
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#define RCAR_I2C_ICCCR_CDF_100_KHZ 6
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#define RCAR_I2C_ICCCR_CDF_400_KHZ 6
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#define RCAR_I2C_ICCCR_SCGD_100_KHZ 21
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#define RCAR_I2C_ICCCR_SCGD_400_KHZ 3
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#define MAX_WAIT_US 100
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static uint32_t i2c_rcar_read(const struct i2c_rcar_cfg *config,
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uint32_t offs)
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{
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return sys_read32(config->reg_addr + offs);
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}
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static void i2c_rcar_write(const struct i2c_rcar_cfg *config,
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uint32_t offs, uint32_t value)
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{
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sys_write32(value, config->reg_addr + offs);
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}
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static void i2c_rcar_isr(const struct device *dev)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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struct i2c_rcar_data *data = dev->data;
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if (((i2c_rcar_read(config, RCAR_I2C_ICMSR)) & data->status_mask) ==
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data->status_mask) {
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k_sem_give(&data->int_sem);
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i2c_rcar_write(config, RCAR_I2C_ICMIER, 0);
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}
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}
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static int i2c_rcar_wait_for_state(const struct device *dev, uint8_t mask)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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struct i2c_rcar_data *data = dev->data;
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data->status_mask = mask;
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/* Reset interrupts semaphore */
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k_sem_reset(&data->int_sem);
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/* Enable interrupts */
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i2c_rcar_write(config, RCAR_I2C_ICMIER, mask);
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/* Wait for the interrupts */
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return k_sem_take(&data->int_sem, K_USEC(MAX_WAIT_US));
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}
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static int i2c_rcar_finish(const struct device *dev)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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int ret;
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/* Enable STOP generation */
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i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER | RCAR_I2C_ICMCR_FSB);
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i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
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/* Wait for STOP to be transmitted */
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ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MST);
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i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
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/* Disable STOP generation */
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i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
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return ret;
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}
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static int i2c_rcar_set_addr(const struct device *dev,
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uint8_t chip, uint8_t read)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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/* Set slave address & transfer mode */
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i2c_rcar_write(config, RCAR_I2C_ICMAR, (chip << 1) | read);
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/* Reset */
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i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER | RCAR_I2C_ICMCR_ESG);
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/* Clear Status */
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i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
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/* Wait for address & transfer mode to be transmitted */
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if (read != 0) {
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return i2c_rcar_wait_for_state(dev, RCAR_I2C_MAT | RCAR_I2C_MDR);
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} else {
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return i2c_rcar_wait_for_state(dev, RCAR_I2C_MAT | RCAR_I2C_MDE);
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}
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}
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static int i2c_rcar_transfer_msg(const struct device *dev, struct i2c_msg *msg)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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uint32_t i, reg;
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int ret = 0;
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if ((msg->flags & I2C_MSG_RW_MASK) == I2C_MSG_READ) {
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/* Reading as master */
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i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
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for (i = 0; i < msg->len; i++) {
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if (msg->len - 1 == i) {
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i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER |
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RCAR_I2C_ICMCR_FSB);
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}
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/* Start data reception */
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reg = i2c_rcar_read(config, RCAR_I2C_ICMSR);
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reg &= ~RCAR_I2C_MDR;
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i2c_rcar_write(config, RCAR_I2C_ICMSR, reg);
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/* Wait for data to be received */
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ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MDR);
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if (ret != 0) {
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return ret;
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}
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msg->buf[i] = i2c_rcar_read(config, RCAR_I2C_ICRXD_ICTXD) & 0xff;
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}
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} else {
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/* Writing as master */
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for (i = 0; i < msg->len; i++) {
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i2c_rcar_write(config, RCAR_I2C_ICRXD_ICTXD, msg->buf[i]);
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i2c_rcar_write(config, RCAR_I2C_ICMCR, RCAR_I2C_ICMCR_MASTER);
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/* Start data transmission */
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reg = i2c_rcar_read(config, RCAR_I2C_ICMSR);
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reg &= ~RCAR_I2C_MDE;
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i2c_rcar_write(config, RCAR_I2C_ICMSR, reg);
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/* Wait for all data to be transmitted */
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ret = i2c_rcar_wait_for_state(dev, RCAR_I2C_MDE);
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if (ret != 0) {
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return ret;
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}
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}
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}
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return ret;
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}
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static int i2c_rcar_transfer(const struct device *dev,
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struct i2c_msg *msgs, uint8_t num_msgs,
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uint16_t addr)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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uint16_t timeout = 0;
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int ret;
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if (!num_msgs) {
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return 0;
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}
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/* Wait for the bus to be available */
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while ((i2c_rcar_read(config, RCAR_I2C_ICMCR) & RCAR_I2C_ICMCR_FSDA) && (timeout < 10)) {
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k_busy_wait(USEC_PER_MSEC);
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timeout++;
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}
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if (timeout == 10) {
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return -EIO;
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}
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do {
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/* We are not supporting 10-bit addressing */
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if ((msgs->flags & I2C_MSG_ADDR_10_BITS) == I2C_MSG_ADDR_10_BITS) {
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return -ENOTSUP;
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}
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/* Send slave address */
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if (i2c_rcar_set_addr(dev, addr, !!(msgs->flags & I2C_MSG_READ))) {
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return -EIO; /* No ACK received */
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}
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/* Transfer data */
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if (msgs->len) {
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ret = i2c_rcar_transfer_msg(dev, msgs);
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if (ret != 0) {
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return ret;
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}
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}
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/* Finish the transfer */
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if ((msgs->flags & I2C_MSG_STOP) == I2C_MSG_STOP) {
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ret = i2c_rcar_finish(dev);
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if (ret != 0) {
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return ret;
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}
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}
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/* Next message */
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msgs++;
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num_msgs--;
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} while (num_msgs);
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/* Complete without error */
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return 0;
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}
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static int i2c_rcar_configure(const struct device *dev, uint32_t dev_config)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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uint8_t cdf, scgd;
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/* We only support Master mode */
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if ((dev_config & I2C_MODE_CONTROLLER) != I2C_MODE_CONTROLLER) {
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return -ENOTSUP;
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}
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/* We are not supporting 10-bit addressing */
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if ((dev_config & I2C_ADDR_10_BITS) == I2C_ADDR_10_BITS) {
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return -ENOTSUP;
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}
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switch (I2C_SPEED_GET(dev_config)) {
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case I2C_SPEED_STANDARD:
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/* Use recommended value for 100 kHz bus */
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cdf = RCAR_I2C_ICCCR_CDF_100_KHZ;
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scgd = RCAR_I2C_ICCCR_SCGD_100_KHZ;
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break;
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case I2C_SPEED_FAST:
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/* Use recommended value for 400 kHz bus */
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cdf = RCAR_I2C_ICCCR_CDF_400_KHZ;
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scgd = RCAR_I2C_ICCCR_SCGD_400_KHZ;
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break;
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default:
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return -ENOTSUP;
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}
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/* Setting ICCCR to recommended value */
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i2c_rcar_write(config, RCAR_I2C_ICCCR, (scgd << 3) | cdf);
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/* Reset slave mode */
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i2c_rcar_write(config, RCAR_I2C_ICSIER, 0);
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i2c_rcar_write(config, RCAR_I2C_ICSAR, 0);
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i2c_rcar_write(config, RCAR_I2C_ICSCR, 0);
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i2c_rcar_write(config, RCAR_I2C_ICSSR, 0);
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/* Reset master mode */
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i2c_rcar_write(config, RCAR_I2C_ICMIER, 0);
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i2c_rcar_write(config, RCAR_I2C_ICMCR, 0);
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i2c_rcar_write(config, RCAR_I2C_ICMSR, 0);
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i2c_rcar_write(config, RCAR_I2C_ICMAR, 0);
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return 0;
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}
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static int i2c_rcar_init(const struct device *dev)
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{
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const struct i2c_rcar_cfg *config = dev->config;
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struct i2c_rcar_data *data = dev->data;
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uint32_t bitrate_cfg;
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int ret;
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k_sem_init(&data->int_sem, 0, 1);
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ret = clock_control_on(config->clock_dev,
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(clock_control_subsys_t *)&config->mod_clk);
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if (ret != 0) {
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return ret;
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}
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bitrate_cfg = i2c_map_dt_bitrate(config->bitrate);
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ret = i2c_rcar_configure(dev, I2C_MODE_CONTROLLER | bitrate_cfg);
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if (ret != 0) {
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return ret;
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}
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config->init_func(dev);
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return 0;
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}
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static const struct i2c_driver_api i2c_rcar_driver_api = {
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.configure = i2c_rcar_configure,
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.transfer = i2c_rcar_transfer,
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};
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/* Device Instantiation */
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#define I2C_RCAR_INIT(n) \
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static void i2c_rcar_##n##_init(const struct device *dev); \
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static const struct i2c_rcar_cfg i2c_rcar_cfg_##n = { \
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.reg_addr = DT_INST_REG_ADDR(n), \
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.init_func = i2c_rcar_##n##_init, \
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.clock_dev = DEVICE_DT_GET(DT_INST_CLOCKS_CTLR(n)), \
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.bitrate = DT_INST_PROP(n, clock_frequency), \
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.mod_clk.module = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 0, module), \
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.mod_clk.domain = \
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DT_INST_CLOCKS_CELL_BY_IDX(n, 0, domain), \
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}; \
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\
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static struct i2c_rcar_data i2c_rcar_data_##n; \
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\
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I2C_DEVICE_DT_INST_DEFINE(n, \
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i2c_rcar_init, \
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NULL, \
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&i2c_rcar_data_##n, \
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&i2c_rcar_cfg_##n, \
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POST_KERNEL, CONFIG_I2C_INIT_PRIORITY, \
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&i2c_rcar_driver_api \
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); \
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static void i2c_rcar_##n##_init(const struct device *dev) \
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{ \
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IRQ_CONNECT(DT_INST_IRQN(n), \
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0, \
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i2c_rcar_isr, \
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DEVICE_DT_INST_GET(n), 0); \
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\
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irq_enable(DT_INST_IRQN(n)); \
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}
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DT_INST_FOREACH_STATUS_OKAY(I2C_RCAR_INIT)
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