zephyr/drivers/interrupt_controller/Kconfig.gic
Neil Armstrong a737999b5b interrupt_controller: gicv3: add Interrupt Translation Service support
This implements support for the optional Interrupt Translation Service
(ITS) module of the GICv3 Interrupt Controller.

The current implementation is designed for MSI/MSI-X interrupt delivery
in mind.
The gicv3 driver calls each ITS INVALL command when LPI interrupts are
enabled/disabled.
A simple atomic integer is used to allocate unique LPI INTIDs to ITS
users.
CPUs numbers are directly mapped as ICIDs into the Collections Table.

As a limitation it doesn't support indirect Device table to simplify
implementation but may use a large amount of memory.

INV, DISCARD, MOVI and MOVALL commands are not implemented.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2021-09-28 19:45:29 -04:00

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# ARM Generic Interrupt Controller (GIC) configuration
# Copyright (c) 2019 Stephanos Ioannidis <root@stephanos.io>
# SPDX-License-Identifier: Apache-2.0
if CPU_CORTEX
config GIC
bool
config GIC_V1
bool
select GIC
help
The ARM Generic Interrupt Controller v1 (e.g. PL390) works with the
ARM Cortex-family processors.
config GIC_V2
bool
select GIC
help
The ARM Generic Interrupt Controller v2 (e.g. GIC-400) works with the
ARM Cortex-family processors.
config GIC_V3
bool
select GIC
help
The ARM Generic Interrupt Controller v3 (e.g. GIC-500 and GIC-600)
works with the ARM Cortex-family processors.
config GIC_VER
int
depends on GIC
default 1 if GIC_V1
default 2 if GIC_V2
default 3 if GIC_V3
config GIC_SINGLE_SECURITY_STATE
bool
depends on GIC_V3
help
Some ARM Cortex-family processors only supports single security
state.
config GIC_V3_ITS
bool "GIC v3 Interrupt Translation Service"
depends on GIC_V3
# ITS generates Non-secure Group 1 LPI interrupts, requiring EL1NS
select ARMV8_A_NS
select DYNAMIC_INTERRUPTS
help
Support for the optional Interrupt Translation Service used to translate
hardware interrupt from PCIe MSI messages for example.
endif # CPU_CORTEX