8185faa0cb
On S32K344, the offset in memory map between each channel is 0x4000 for most channels, but there is specific case is between channel 11 and 12 which is 0x1D4000 instead. As a consequence, 32 channels are divided to two parts: one starts from channel 0 -> 11. The other is from channel 128 to 145. The channel gap is from 12 -> 127. For user and data structures in shim driver, the channel's value comes from 0 --> 31. Above constraint will be counted when interact with the mcux sdk Beside that, the DMAMUX register in this platform is very specific, not in identical with DMAMUX channel, so shim driver is updated to cover this case Signed-off-by: Dat Nguyen Duy <dat.nguyenduy@nxp.com>
45 lines
1.1 KiB
Plaintext
45 lines
1.1 KiB
Plaintext
# DMA configuration options
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# Copyright (c) 2020, NXP
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# SPDX-License-Identifier: Apache-2.0
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config DMA_MCUX_EDMA
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bool "MCUX DMA driver"
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default y
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depends on DT_HAS_NXP_MCUX_EDMA_ENABLED
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imply NOCACHE_MEMORY if HAS_MCUX_CACHE
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help
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DMA driver for MCUX series SoCs.
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config DMA_MCUX_EDMA_V3
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bool "MCUX DMA v3 driver"
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default y
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depends on DT_HAS_NXP_MCUX_EDMA_V3_ENABLED
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help
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DMA version 3 driver for MCUX series SoCs.
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if DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3
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config DMA_TCD_QUEUE_SIZE
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int "number of TCD in a queue for SG mode"
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default 2
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help
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number of TCD in a queue for SG mode
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config DMA_MCUX_TEST_SLOT_START
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int "test slot start num"
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depends on (SOC_SERIES_KINETIS_K6X || SOC_SERIES_KINETIS_KE1XF || SOC_SERIES_S32K3_M7)
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default 58 if SOC_SERIES_KINETIS_K6X
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default 60 if SOC_SERIES_KINETIS_KE1XF
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default 62 if SOC_SERIES_S32K3_M7
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help
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test slot start num
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config DMA_MCUX_USE_DTCM_FOR_DMA_DESCRIPTORS
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bool "Use DTCM for DMA descriptors"
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help
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When this option is activated, the descriptors for DMA transfer are
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located in the DTCM (Data Tightly Coupled Memory).
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endif # DMA_MCUX_EDMA || DMA_MCUX_EDMA_V3
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