Henri Xavier 45af717a66 arch/arm64: Implement ASID support in ARM64 MMU ... Improves context-switch performance. TLB invalidation and the nG bit are used conservatively. This could be improved in future work. Tested with tests/benchmarks/sched_userspace: BEFORE: ``` Swapping 2 threads: 161562583 cyc & 1000000 rounds -> 1615 ns per ctx Swapping 8 threads: 161569289 cyc & 1000000 rounds -> 1615 ns per ctx Swapping 16 threads: 161649163 cyc & 1000000 rounds -> 1616 ns per ctx Swapping 32 threads: 163487880 cyc & 1000000 rounds -> 1634 ns per ctx ``` AFTER: ``` Swapping 2 threads: 18129207 cyc & 1000000 rounds -> 181 ns per ctx Swapping 8 threads: 49702891 cyc & 1000000 rounds -> 497 ns per ctx Swapping 16 threads: 55898650 cyc & 1000000 rounds -> 558 ns per ctx Swapping 32 threads: 58059704 cyc & 1000000 rounds -> 580 ns per ctx ``` Signed-off-by: Henri Xavier <datacomos@huawei.com>		2022-12-13 17:21:11 +09:00
..
arc	arc: cache: Rework cache API	2022-12-01 13:40:56 -05:00
arm	arm: aarch32: config static regions with MPU disabled	2022-12-12 10:39:31 +01:00
arm64	arch/arm64: Implement ASID support in ARM64 MMU	2022-12-13 17:21:11 +09:00
common	include: add missing irq.h include	2022-10-11 18:05:17 +02:00
mips	include: types: remove ulong_t	2022-09-06 18:16:33 +02:00
nios2	arch: comply to coding guidelines MISRA C:2012 Rule 14.4	2022-07-20 09:28:38 -05:00
posix	arch: posix: Declare _posix_zephyr_main with int return type	2022-11-05 16:41:45 +09:00
riscv	Revert "riscv: PMP-based stack guard is incompatible with stack sentinel"	2022-10-25 10:53:34 +02:00
sparc	SPARC: reduce z_thread_entry_wrapper	2022-08-03 12:05:49 +02:00
x86	cache: Rework cache API	2022-12-01 13:40:56 -05:00
xtensa	xtensa: remove xtensa asm unused header	2022-11-22 12:45:33 +09:00
CMakeLists.txt	cmake: fix include directories to work with out-of-tree arch	2020-08-05 08:06:07 -04:00
Kconfig	cache: Rework cache API	2022-12-01 13:40:56 -05:00