da5030eae1
SPI configuration did not set bit ordering or more importantly the clock polarity which seemed to be misconfigured. Setting this corrects one more quirk when working with this part on the TDK Robokit1 Signed-off-by: Tom Burdick <thomas.burdick@intel.com>
311 lines
9 KiB
C
311 lines
9 KiB
C
/* TI ADS7052 ADC
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*
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* Copyright (c) 2023 Google, LLC
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_ads7052
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#include <zephyr/device.h>
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#include <zephyr/drivers/adc.h>
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#include <zephyr/drivers/spi.h>
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#include <zephyr/logging/log.h>
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#include <zephyr/kernel.h>
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LOG_MODULE_REGISTER(adc_ads7052);
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#define ADC_CONTEXT_USES_KERNEL_TIMER
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#include "adc_context.h"
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#define ADS7052_RESOLUTION 14U
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struct ads7052_config {
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struct spi_dt_spec bus;
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uint8_t channels;
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};
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struct ads7052_data {
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struct adc_context ctx;
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const struct device *dev;
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uint16_t *buffer;
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uint16_t *repeat_buffer;
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uint8_t channels;
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struct k_thread thread;
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struct k_sem sem;
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K_KERNEL_STACK_MEMBER(stack, CONFIG_ADC_ADS7052_ACQUISITION_THREAD_STACK_SIZE);
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};
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static int adc_ads7052_channel_setup(const struct device *dev,
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const struct adc_channel_cfg *channel_cfg)
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{
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const struct ads7052_config *config = dev->config;
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if (channel_cfg->gain != ADC_GAIN_1) {
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LOG_ERR("unsupported channel gain '%d'", channel_cfg->gain);
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return -ENOTSUP;
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}
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if (channel_cfg->reference != ADC_REF_VDD_1) {
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LOG_ERR("unsupported channel reference '%d'", channel_cfg->reference);
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return -ENOTSUP;
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}
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if (channel_cfg->acquisition_time != ADC_ACQ_TIME_DEFAULT) {
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LOG_ERR("unsupported acquisition_time '%d'", channel_cfg->acquisition_time);
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return -ENOTSUP;
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}
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if (channel_cfg->channel_id >= config->channels) {
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LOG_ERR("unsupported channel id '%d'", channel_cfg->channel_id);
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return -ENOTSUP;
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}
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return 0;
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}
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static int ads7052_validate_buffer_size(const struct device *dev,
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const struct adc_sequence *sequence)
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{
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uint8_t channels = 0;
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size_t needed;
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channels = POPCOUNT(sequence->channels);
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needed = channels * sizeof(uint16_t);
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if (sequence->options) {
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needed *= (1 + sequence->options->extra_samplings);
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}
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if (sequence->buffer_size < needed) {
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return -ENOMEM;
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}
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return 0;
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}
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/**
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* @brief Send ADS7052 Offset calibration request
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*
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* On power-up, the host must provide 24 SCLKs in the first serial transfer to enter the OFFCAL
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* state. During normal operation, the host must provide 64 SCLKs in the serial transfer frame to
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* enter the OFFCAL state.
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*/
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static int ads7052_send_calibration(const struct device *dev, bool power_up)
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{
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const struct ads7052_config *config = dev->config;
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int err;
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uint8_t sclks_needed = power_up ? 24 : 64;
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uint8_t num_bytes = sclks_needed / 8;
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uint8_t tx_bytes[8] = {0};
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const struct spi_buf tx_buf = {.buf = tx_bytes, .len = num_bytes};
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const struct spi_buf_set tx = {.buffers = &tx_buf, .count = 1};
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err = spi_write_dt(&config->bus, &tx);
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return err;
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}
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static int ads7052_start_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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const struct ads7052_config *config = dev->config;
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struct ads7052_data *data = dev->data;
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int err;
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if (sequence->resolution != ADS7052_RESOLUTION) {
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LOG_ERR("unsupported resolution %d", sequence->resolution);
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return -ENOTSUP;
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}
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if (find_msb_set(sequence->channels) > config->channels) {
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LOG_ERR("unsupported channels in mask: 0x%08x", sequence->channels);
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return -ENOTSUP;
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}
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if (sequence->calibrate) {
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ads7052_send_calibration(dev, false);
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}
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err = ads7052_validate_buffer_size(dev, sequence);
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if (err) {
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LOG_ERR("buffer size too small");
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return err;
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}
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data->buffer = sequence->buffer;
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adc_context_start_read(&data->ctx, sequence);
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return adc_context_wait_for_completion(&data->ctx);
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}
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static int adc_ads7052_read_async(const struct device *dev, const struct adc_sequence *sequence,
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struct k_poll_signal *async)
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{
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struct ads7052_data *data = dev->data;
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int error;
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adc_context_lock(&data->ctx, async ? true : false, async);
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error = ads7052_start_read(dev, sequence);
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adc_context_release(&data->ctx, error);
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return error;
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}
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static int adc_ads7052_read(const struct device *dev, const struct adc_sequence *sequence)
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{
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return adc_ads7052_read_async(dev, sequence, NULL);
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}
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static void adc_context_start_sampling(struct adc_context *ctx)
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{
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struct ads7052_data *data = CONTAINER_OF(ctx, struct ads7052_data, ctx);
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data->channels = ctx->sequence.channels;
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data->repeat_buffer = data->buffer;
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k_sem_give(&data->sem);
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}
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static void adc_context_update_buffer_pointer(struct adc_context *ctx, bool repeat_sampling)
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{
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struct ads7052_data *data = CONTAINER_OF(ctx, struct ads7052_data, ctx);
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if (repeat_sampling) {
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data->buffer = data->repeat_buffer;
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}
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}
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/**
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* @brief Get a 14-bit integer from raw ADC data.
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*
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* @param src Location of the big-endian 14-bit integer to get.
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*
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* @return 14-bit integer in host endianness.
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*/
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static inline int ads7052_get_be14(const uint8_t src[2])
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{
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return ((src[0] & 0x7F) << 7) | (src[1] >> 1);
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}
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/**
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* @brief Read ADS7052 over SPI interface
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*
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* A leading 0 is output on the SDO pin on the CS falling edge.
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* The most significant bit (MSB) of the output data is launched on the SDO pin on the rising edge
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* after the first SCLK falling edge. Subsequent output bits are launched on the subsequent rising
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* edges provided on SCLK. When all 14 output bits are shifted out, the device outputs 0's on the
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* subsequent SCLK rising edges. The device enters the ACQ state after 18 clocks and a minimum time
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* of tACQ must be provided for acquiring the next sample. If the device is provided with less than
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* 18 SCLK falling edges in the present serial transfer frame, the device provides an invalid
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* conversion result in the next serial transfer frame
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*/
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static int ads7052_read_channel(const struct device *dev, uint8_t channel, uint16_t *result)
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{
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const struct ads7052_config *config = dev->config;
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int err;
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uint8_t rx_bytes[3];
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const struct spi_buf rx_buf[1] = {{.buf = rx_bytes, .len = sizeof(rx_bytes)}};
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const struct spi_buf_set rx = {.buffers = rx_buf, .count = ARRAY_SIZE(rx_buf)};
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err = spi_read_dt(&config->bus, &rx);
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if (err) {
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return err;
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}
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*result = ads7052_get_be14(rx_bytes);
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*result &= BIT_MASK(ADS7052_RESOLUTION);
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return 0;
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}
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static void ads7052_acquisition_thread(struct ads7052_data *data)
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{
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uint16_t result = 0;
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uint8_t channel;
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int err = 0;
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err = ads7052_send_calibration(data->dev, true);
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if (err) {
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LOG_ERR("failed to send powerup sequence (err %d)", err);
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}
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while (true) {
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k_sem_take(&data->sem, K_FOREVER);
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while (data->channels != 0) {
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channel = find_lsb_set(data->channels) - 1;
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LOG_DBG("reading channel %d", channel);
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err = ads7052_read_channel(data->dev, channel, &result);
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if (err) {
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LOG_ERR("failed to read channel %d (err %d)", channel, err);
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adc_context_complete(&data->ctx, err);
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break;
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}
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LOG_DBG("read channel %d, result = %d", channel, result);
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*data->buffer++ = result;
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WRITE_BIT(data->channels, channel, 0);
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}
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adc_context_on_sampling_done(&data->ctx, data->dev);
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}
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}
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static int adc_ads7052_init(const struct device *dev)
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{
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const struct ads7052_config *config = dev->config;
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struct ads7052_data *data = dev->data;
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data->dev = dev;
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adc_context_init(&data->ctx);
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k_sem_init(&data->sem, 0, 1);
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if (!spi_is_ready_dt(&config->bus)) {
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LOG_ERR("SPI bus %s not ready", config->bus.bus->name);
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return -ENODEV;
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}
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k_thread_create(&data->thread, data->stack,
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CONFIG_ADC_ADS7052_ACQUISITION_THREAD_STACK_SIZE,
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(k_thread_entry_t)ads7052_acquisition_thread, data, NULL, NULL,
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CONFIG_ADC_ADS7052_ACQUISITION_THREAD_PRIO, 0, K_NO_WAIT);
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adc_context_unlock_unconditionally(&data->ctx);
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return 0;
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}
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static const struct adc_driver_api ads7052_api = {
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.channel_setup = adc_ads7052_channel_setup,
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.read = adc_ads7052_read,
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#ifdef CONFIG_ADC_ASYNC
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.read_async = adc_ads7052_read_async,
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#endif
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};
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#define ADC_ADS7052_SPI_CFG \
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SPI_OP_MODE_MASTER | SPI_MODE_CPOL | SPI_MODE_CPHA | SPI_WORD_SET(8) | SPI_TRANSFER_MSB
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#define ADC_ADS7052_INIT(n) \
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\
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static const struct ads7052_config ads7052_cfg_##n = { \
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.bus = SPI_DT_SPEC_INST_GET(n, ADC_ADS7052_SPI_CFG, 1U), \
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.channels = 1, \
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}; \
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\
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static struct ads7052_data ads7052_data_##n = { \
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ADC_CONTEXT_INIT_TIMER(ads7052_data_##n, ctx), \
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ADC_CONTEXT_INIT_LOCK(ads7052_data_##n, ctx), \
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ADC_CONTEXT_INIT_SYNC(ads7052_data_##n, ctx), \
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}; \
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\
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DEVICE_DT_INST_DEFINE(n, adc_ads7052_init, NULL, &ads7052_data_##n, &ads7052_cfg_##n, \
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POST_KERNEL, CONFIG_ADC_ADS7052_INIT_PRIORITY, &ads7052_api);
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DT_INST_FOREACH_STATUS_OKAY(ADC_ADS7052_INIT)
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